rpi: Allow using PL011 UART for RPi3/RPi4

The Broadcom 283x SoCs feature multiple UARTs: the mostly used
"Mini-UART", which is an 8250 compatible IP, and at least one PL011.
While the 8250 is usuall

rpi: Allow using PL011 UART for RPi3/RPi4

The Broadcom 283x SoCs feature multiple UARTs: the mostly used
"Mini-UART", which is an 8250 compatible IP, and at least one PL011.
While the 8250 is usually used for serial console purposes, it suffers
from a design flaw, where its clock depends on the VPU clock, which can
change at runtime. This will reliably mess up the baud rate.
To avoid this problem, people might choose to use the PL011 UART for
the serial console, which is pin-mux'ed to the very same GPIO pins.
This can be done by adding "miniuart-bt" to the "dtoverlay=" line in
config.txt.

To prepare for this situation, use the newly gained freedom of sharing
one console_t pointer across different UART drivers, to introduce the
option of choosing the PL011 for the console.

This is for now hard-coded to choose the Mini-UART by default.
A follow-up patch will introduce automatic detection.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I8cf2522151e09ff4ff94a6d396aec6fc4b091a05

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rpi3: console: Use same "clock-less" setup scheme as RPi4

In the wake of the upcoming unification of the console setup code
between RPi3 and RPi4, extend the "clock-less" setup scheme to the
RPi3. T

rpi3: console: Use same "clock-less" setup scheme as RPi4

In the wake of the upcoming unification of the console setup code
between RPi3 and RPi4, extend the "clock-less" setup scheme to the
RPi3. This avoid programming any clocks or baud rate registers,
which makes the port more robust against GPU firmware changes.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ida83a963bb18a878997e9cbd55f8ceac6a2e1c1f

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rpi3: gpio: Simplify GPIO setup

There is really no reason to use and pass around a struct when its only
member is the (fixed) base address.

Remove the struct and just use the base address on its ow

rpi3: gpio: Simplify GPIO setup

There is really no reason to use and pass around a struct when its only
member is the (fixed) base address.

Remove the struct and just use the base address on its own inside the
GPIO driver. Then set the base address automatically.

This simplifies GPIO setup for users, which now don't need to deal with
zeroing a struct and setting the base address anymore.

Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Implement SMCCC_ARCH_SOC_ID SMC call

Implemented SMCCC_ARCH_SOC_ID call in order to get below
SOC information:

1. SOC revision
2. SOC version

Implementation done using below SMCCC specification do

Implement SMCCC_ARCH_SOC_ID SMC call

Implemented SMCCC_ARCH_SOC_ID call in order to get below
SOC information:

1. SOC revision
2. SOC version

Implementation done using below SMCCC specification document:
https://developer.arm.com/docs/den0028/c

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie0595f1c345a6429a6fb4a7f05534a0ca9c9a48b

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plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE

Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A53
doesn't make sense (since UART pinmux/clock configuration is appli

plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE

Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A53
doesn't make sense (since UART pinmux/clock configuration is applied
for UART only when DEBUG_CONSOLE_A53 is enabled).

Enable DEBUG_CONSOLE_A53 if DEBUG_CONSOLE is enabled.

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I8ca411d5544658b9bcc39e5340ec042c51088b96

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plat: imx: imx8qm: provide debug uart num as build param

This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
provid

plat: imx: imx8qm: provide debug uart num as build param

This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
provided via DT) to set this configuration during compile time via
IMX_DEBUG_UART build flag.

Usage:
$ make PLAT=imx8qm IMX_DEBUG_UART=1 bl31

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: Ib5f5dd81ba0c8ad2b2dc5647ec75629072f511c5

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plat: imx: imx8_iomux: fix shift-overflow errors

This fixes shift overflow errors, when compiled with CONSOLE_DEBUG
support:

plat/imx/common/include/imx8_iomux.h:11:35: error: result of ‘1 << 31’
r

plat: imx: imx8_iomux: fix shift-overflow errors

This fixes shift overflow errors, when compiled with CONSOLE_DEBUG
support:

plat/imx/common/include/imx8_iomux.h:11:35: error: result of ‘1 << 31’
requires 33 bits to represent, but ‘int’ only has 32 bits
[-Werror=shift-overflow=]

Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I0488e22c30314ba27caabc5c767164baa1e8004c

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fconf: Clean Arm IO

Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This
removes the duplicate io_policies and functions definition.

This patch:
- replace arm_io_storage.c

fconf: Clean Arm IO

Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This
removes the duplicate io_policies and functions definition.

This patch:
- replace arm_io_storage.c with the content of arm_fconf_io_storage.c
- rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB.
- use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb.
- propagate DEFINES when parsing dts.
- use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb.
- set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior
of fvp stays the same as it was before the introduction of fconf.

Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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Merge "SPMD: Add support for SPCI_ID_GET" into integration

plat/sgi: Bump bl1 RW limit

Increase bl1 RW limit to allow future development.

Change-Id: I3159b36dbaca798b4c4374c1415cd033d6586388
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Merge "juno/sgm: Maximize space allocated to SCP_BL2" into integration

SPMD: Add support for SPCI_ID_GET

This patch introduces the `SPCI_ID_GET` interface which will return the
ID of the calling SPCI component. Returns 0 for requests from the
non-secure world and the S

SPMD: Add support for SPCI_ID_GET

This patch introduces the `SPCI_ID_GET` interface which will return the
ID of the calling SPCI component. Returns 0 for requests from the
non-secure world and the SPCI component ID as specified in the manifest
for secure world requests.

Change-Id: Icf81eb1d0e1d7d5c521571e04972b6e2d356e0d1
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>

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Merge changes from topic "mp/enhanced_pal_hw" into integration

* changes:
plat/arm/fvp: populate pwr domain descriptor dynamically
fconf: Extract topology node properties from HW_CONFIG dtb
fc

Merge changes from topic "mp/enhanced_pal_hw" into integration

* changes:
plat/arm/fvp: populate pwr domain descriptor dynamically
fconf: Extract topology node properties from HW_CONFIG dtb
fconf: necessary modifications to support fconf in BL31 & SP_MIN
fconf: enhancements to firmware configuration framework

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juno/sgm: Maximize space allocated to SCP_BL2

To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its c

juno/sgm: Maximize space allocated to SCP_BL2

To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its current (mostly) arbitrary address to the beginning
of the non-shared trusted SRAM.

Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434
Signed-off-by: Chris Kay <chris.kay@arm.com>

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board/rddaniel: add NSAID sources for TZC400 driver

Add CLCD, HDLCD, PCI and VIRTIO devices as source interfaces for TZC
filter unit to enable DMA for these devices.

Change-Id: Ifad2e56b18605311936

board/rddaniel: add NSAID sources for TZC400 driver

Add CLCD, HDLCD, PCI and VIRTIO devices as source interfaces for TZC
filter unit to enable DMA for these devices.

Change-Id: Ifad2e56b18605311936e03cfcccda573cac7e60a
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

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Merge "n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag" into integration

plat/arm/fvp: populate pwr domain descriptor dynamically

The motivation behind this patch and following patches is to extract
information about the platform in runtime rather than depending on
compi

plat/arm/fvp: populate pwr domain descriptor dynamically

The motivation behind this patch and following patches is to extract
information about the platform in runtime rather than depending on
compile time macros such as FVP_CLUSTER_COUNT. This partially enables
us to use a single binary for a family of platforms which all have
similar hardware capabilities but differ in configurations.

we populate the data structure describing the power domain hierarchy
of the platform dynamically by querying the number of clusters and cpus
using fconf getter APIs. Compile time macro such as FVP_CLUSTER_COUNT
is still needed as it determines the size of related data structures.

Note that the cpu-map node in HW_CONFIG dts represents a logical
hierarchy of power domains of CPU. However, in reality, the power
domains may not have been physically built in such hierarchy.

Change-Id: Ibcbb5ca7b2c969f8ad03ab2eab289725245af7a9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Tegra210: Remove "unsupported func ID" error msg

The platform sip is reporting a "unsupported function ID" if the
smc function id is not pmc command. When actually the smc function id
could be speci

Tegra210: Remove "unsupported func ID" error msg

The platform sip is reporting a "unsupported function ID" if the
smc function id is not pmc command. When actually the smc function id
could be specific to the tegra sip handler.
This patch removes the error reported.

Change-Id: Ia3c8545d345746c5eea6d75b9e6957ca23ae9ca3
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Tegra210: support for secure physical timer

This patch enables on-chip timer1 interrupts for Tegra210 platforms.

Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e
Signed-off-by: Varun Wadekar <v

Tegra210: support for secure physical timer

This patch enables on-chip timer1 interrupts for Tegra210 platforms.

Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: export handlers to read/write SMMU registers

This patch exports the SMMU register read/write handlers for platforms.

Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da
Signed-off-by:

Tegra: smmu: export handlers to read/write SMMU registers

This patch exports the SMMU register read/write handlers for platforms.

Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: smmu: remove context save sequence

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS

Tegra: smmu: remove context save sequence

SMMU and MC registers are saved as part of the System Suspend sequence.
The register list includes some NS world SMMU registers that need to be
saved by NS world software instead. All that remains as a result are
the MC registers.

This patch moves code to MC file as a result and renames all the
variables and defines to use the MC prefix instead of SMMU. The
Tegra186 and Tegra194 platform ports are updated to provide the MC
context register list to the parent driver. The memory required for
context save is reduced due to removal of the SMMU registers.

Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, wa

Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.

Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: memctrl: lock some more MC SID security configs

The platform code already contains the initial set of MC SID
security configs to be locked during boot. This patch adds some
more configs to

Tegra194: memctrl: lock some more MC SID security configs

The platform code already contains the initial set of MC SID
security configs to be locked during boot. This patch adds some
more configs to the list. Since the reset value of these registers
is already as per expectations, there is no need to change it.

MC SID security configs
- PTCR,
- MIU6R, MIU6W, MIU7R, MIU7W,
- MPCORER, MPCOREW,
- NVDEC1SRD, NVDEC1SRD1, NVDEC1SWR.

Change-Id: Ia9a1f6a6b6d34fb2787298651f7a4792a40b88ab
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: add SE support to generate SHA256 of TZRAM

The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
s

Tegra194: add SE support to generate SHA256 of TZRAM

The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
memory loses power when we enter System Suspend and so its contents are
stored to TZDRAM, before entry. This opens up an attack vector where the
TZDRAM contents might be tampered with when we are in the System Suspend
mode. To mitigate this attack the SE engine calculates the hash of entire
TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
WB0 code will validate the TZDRAM and match the hash with the one in PMC
scratch.

This patch adds driver for the SE engine, with APIs to calculate the hash
and store to PMC scratch registers.

Change-Id: I04cc0eb7f54c69d64b6c34fc2ff62e4cfbdd43b2
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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Tegra194: store TZDRAM base/size to scratch registers

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify in

Tegra194: store TZDRAM base/size to scratch registers

This patch saves the TZDRAM base and size values to secure scratch
registers, for the WB0. The WB0 reads these values and uses them to
verify integrity of the TZDRAM aperture.

Change-Id: I2f5fd11c87804d20e2698de33be977991c9f6f33
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>

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