xref: /rk3399_ARM-atf/plat/arm/board/arm_fpga/fpga_bl31_setup.c (revision 5cfe699f2bcff007a51bea3b093fd869ef7480cf)
1 /*
2  * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <plat/common/platform.h>
10 #include <platform_def.h>
11 
12 #include "fpga_private.h"
13 
14 static entry_point_info_t bl33_image_ep_info;
15 
16 uintptr_t plat_get_ns_image_entrypoint(void)
17 {
18 #ifdef PRELOADED_BL33_BASE
19 	return PRELOADED_BL33_BASE;
20 #else
21 	return 0;
22 #endif
23 }
24 
25 uint32_t fpga_get_spsr_for_bl33_entry(void)
26 {
27 	return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
28 }
29 
30 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
31 				u_register_t arg2, u_register_t arg3)
32 {
33 	fpga_console_init();
34 
35 	bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
36 	bl33_image_ep_info.spsr = fpga_get_spsr_for_bl33_entry();
37 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
38 
39 	/* Set x0-x3 for the primary CPU as expected by the kernel */
40 	bl33_image_ep_info.args.arg0 = (u_register_t)FPGA_PRELOADED_DTB_BASE;
41 	bl33_image_ep_info.args.arg1 = 0U;
42 	bl33_image_ep_info.args.arg2 = 0U;
43 	bl33_image_ep_info.args.arg3 = 0U;
44 }
45 
46 void bl31_plat_arch_setup(void)
47 {
48 }
49 
50 void bl31_platform_setup(void)
51 {
52 	/* TODO: initialize GIC and timer using the specifications of the FPGA image */
53 }
54 
55 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
56 {
57 	entry_point_info_t *next_image_info;
58 	next_image_info = &bl33_image_ep_info;
59 
60 	/* Only expecting BL33: the kernel will run in EL2NS */
61 	assert(type == NON_SECURE);
62 
63 	/* None of the images can have 0x0 as the entrypoint */
64 	if (next_image_info->pc) {
65 		return next_image_info;
66 	} else {
67 		return NULL;
68 	}
69 }
70 
71 unsigned int plat_get_syscnt_freq2(void)
72 {
73 	/*
74 	 * TODO: return the frequency of the System Counter as configured by the
75 	 * FPGA image
76 	 */
77 	return 0;
78 }
79 
80 void bl31_plat_enable_mmu(uint32_t flags)
81 {
82 	/* TODO: determine if MMU needs to be enabled */
83 }
84