1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include "../fpga_def.h" 12 13 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 14 15 #define PLATFORM_LINKER_ARCH aarch64 16 17 #define PLATFORM_STACK_SIZE UL(0x800) 18 19 #define CACHE_WRITEBACK_SHIFT U(6) 20 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 21 22 #define PLATFORM_CORE_COUNT \ 23 (FPGA_MAX_CLUSTER_COUNT * FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU) 24 25 #define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + \ 26 PLATFORM_CORE_COUNT) + 1 27 28 #define BL31_BASE UL(0x80000000) 29 #define BL31_LIMIT UL(0x80100000) 30 31 #define PLAT_MAX_RET_STATE 1 32 #define PLAT_MAX_OFF_STATE 2 33 34 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 35 36 #define PLAT_FPGA_HOLD_ENTRY_SHIFT 3 37 #define PLAT_FPGA_HOLD_STATE_WAIT 0 38 #define PLAT_FPGA_HOLD_STATE_GO 1 39 40 #define PLAT_FPGA_CONSOLE_BAUDRATE 38400 41 42 #endif 43