Merge changes from topic "mbox-patches" into integration

* changes:
intel: common: Fix non-MISRA compliant code v2
intel: mailbox: Fix non-MISRA compliant code
intel: mailbox: Mailbox error re

Merge changes from topic "mbox-patches" into integration

* changes:
intel: common: Fix non-MISRA compliant code v2
intel: mailbox: Fix non-MISRA compliant code
intel: mailbox: Mailbox error recovery handling
intel: mailbox: Enable sending large mailbox command
intel: mailbox: Use retry count in mailbox poll
intel: mailbox: Ensure time out duration is predictive
intel: mailbox: Read mailbox response even there is an error
intel: mailbox: Driver now handles larger response
intel: common: Change how mailbox handles job id & buffer
intel: common: Improve readability of mailbox read response
intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
intel: common: Remove urgent from mailbox async
intel: common: Improve mailbox driver readability

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Use constant stack size with RECLAIM_INIT_CODE

Currently, when RECLAIM_INIT_CODE is set, the
stacks are scaled to ensure that the entirety
of the init section can be reclaimed as stack.

This causes

Use constant stack size with RECLAIM_INIT_CODE

Currently, when RECLAIM_INIT_CODE is set, the
stacks are scaled to ensure that the entirety
of the init section can be reclaimed as stack.

This causes an issue in lib/psci/aarch64/psci_helpers.S,
where the stack size is used for cache operations in
psci_do_pwrdown_cache_maintenance(). If the stacks
are scaled, then the PSCI code may fail to invalidate
some of the stack memory before power down.

Resizing stacks is also not good for stability in general,
since code that works with a small number of cores may
overflow the stack when the number of cores is increased.

Change to make every stack be PLATFORM_STACK_SIZE big,
and allow the total stack to be smaller than the
init section.

Any pages of the init section not reclaimed as
stack will be set to read-only and execute-never,
for security.

Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8
Signed-off-by: David Horstmann <david.horstmann@arm.com>

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Merge changes from topic "mbox-patches" into integration

* changes:
intel: common: Clean up mailbox and sip header
intel: clear 'PLAT_SEC_ENTRY' in early platform setup

Merge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration

* changes:
mediatek: mt8192: add timer support
mediatek: mt8192: Add reboot function for PSCI
mediatek: mt8192: add sys_c

Merge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration

* changes:
mediatek: mt8192: add timer support
mediatek: mt8192: Add reboot function for PSCI
mediatek: mt8192: add sys_cirq driver
mediatek: mt8192: add GPIO driver support

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mediatek: mt8192: add timer support

add timer driver.

Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7

mediatek: mt8192: Add reboot function for PSCI

Add system_reset function in psci ops

Change-Id: If85be70b8ae9d6487e02626356f0ff1e78b76de9
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>

mediatek: mt8192: add sys_cirq driver

1.add sys_cirq driver
2.add gic api for cirq

Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b
Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>

Merge "plat: marvell: armada: Fix dependences for target fip" into integration

intel: common: Fix non-MISRA compliant code v2

This patch is used to fix remaining non compliant code for Intel
SoCFPGA's mailbox and sip driver. These changes include:
- Change non-interface requir

intel: common: Fix non-MISRA compliant code v2

This patch is used to fix remaining non compliant code for Intel
SoCFPGA's mailbox and sip driver. These changes include:
- Change non-interface required uint32_t into unsigned int
- Change non-negative variable to unsigned int
- Remove obsolete variable initialization to 0

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5

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intel: mailbox: Fix non-MISRA compliant code

This patch is used to fix remaining non compliant code for Intel
SocFPGA's mailbox driver. These changes include:
- adding integer literal for unsigned c

intel: mailbox: Fix non-MISRA compliant code

This patch is used to fix remaining non compliant code for Intel
SocFPGA's mailbox driver. These changes include:
- adding integer literal for unsigned constant
- fix non-boolean controlling expression
- add braces even on conditional single statement bodies

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0f8fd96a3540f35ee102fd2f2369b76fa73e39e1

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intel: mailbox: Mailbox error recovery handling

Attempt to restart the mailbox if the mailbox driver not able
to write any data into the mailbox command buffer.

Signed-off-by: Chee Hong Ang <chee.h

intel: mailbox: Mailbox error recovery handling

Attempt to restart the mailbox if the mailbox driver not able
to write any data into the mailbox command buffer.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: Ia45291c985844dec9da82839cac701347534d32b

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intel: mailbox: Enable sending large mailbox command

Allow mailbox command that is larger than mailbox command FIFO buffer
size to be sent to SDM in multiple chunks.

Signed-off-by: Abdul Halim, Muh

intel: mailbox: Enable sending large mailbox command

Allow mailbox command that is larger than mailbox command FIFO buffer
size to be sent to SDM in multiple chunks.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I683d5f1d04c4fdf57d11ecae6232b7ed3fc49e26

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intel: mailbox: Use retry count in mailbox poll

Change the main loop inside mailbox poll function from while(1) to a
retry counter named sdm_loop. This is to limit the maximum possible
looping of th

intel: mailbox: Use retry count in mailbox poll

Change the main loop inside mailbox poll function from while(1) to a
retry counter named sdm_loop. This is to limit the maximum possible
looping of the function and prevent unexpected behaviour.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I63afad958fe5f656f6333b60d5a8b4c0ada3b23d

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intel: mailbox: Ensure time out duration is predictive

For each count down of time out counter, wait for number of
miliseconds to ensure the time out duration is predictive.

Signed-off-by: Chee Hon

intel: mailbox: Ensure time out duration is predictive

For each count down of time out counter, wait for number of
miliseconds to ensure the time out duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b

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intel: mailbox: Read mailbox response even there is an error

Mailbox driver should read the response data if the response length
in the response header is non-zero even the response header indicates

intel: mailbox: Read mailbox response even there is an error

Mailbox driver should read the response data if the response length
in the response header is non-zero even the response header indicates
error (non-zero).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640

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intel: mailbox: Driver now handles larger response

This patch factorizes mailbox read response from SDM into a function.
Also fix the logic to support reading larger than 16 words response from
SDM.

intel: mailbox: Driver now handles larger response

This patch factorizes mailbox read response from SDM into a function.
Also fix the logic to support reading larger than 16 words response from
SDM.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5

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intel: common: Change how mailbox handles job id & buffer

This patch modifies several basic mailbox driver features to prepare for
FCS enablement:
- Job id management for asynchronous response
- SDM

intel: common: Change how mailbox handles job id & buffer

This patch modifies several basic mailbox driver features to prepare for
FCS enablement:
- Job id management for asynchronous response
- SDM command buffer full

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2

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Merge "SPMC: adjust device region for first secure partition" into integration

mediatek: mt8192: add GPIO driver support

add GPIO driver

Change-Id: I67a9abef078e7a62b34dfbd366b45c03892800cd
Signed-off-by: Po Xu <jg_poxu@mediatek.com>

intel: common: Clean up mailbox and sip header

Sort and rearrange definitions in both mailbox and sip header to
increase readability and maintainability.

Signed-off-by: Abdul Halim, Muhammad Hadi A

intel: common: Clean up mailbox and sip header

Sort and rearrange definitions in both mailbox and sip header to
increase readability and maintainability.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856

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intel: common: Improve readability of mailbox read response

Rename variables to improve readability of mailbox read response and
mailbox poll response flow.

Signed-off-by: Abdul Halim, Muhammad Had

intel: common: Improve readability of mailbox read response

Rename variables to improve readability of mailbox read response and
mailbox poll response flow.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Icd33ff1d2abb28eeead15e4eb9c7f9629f8cb402

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intel: clear 'PLAT_SEC_ENTRY' in early platform setup

Ensure 'PLAT_SEC_ENTRY' is cleared during early platform
setup. This is to prevent the slave CPU cores jump to the stale
entry point after warm

intel: clear 'PLAT_SEC_ENTRY' in early platform setup

Ensure 'PLAT_SEC_ENTRY' is cleared during early platform
setup. This is to prevent the slave CPU cores jump to the stale
entry point after warm reset when using U-Boot SPL as first
stage boot loader.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a

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intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB

Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher
pre-reserved memory size between Intel service layer and secure monitor
softwar

intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB

Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher
pre-reserved memory size between Intel service layer and secure monitor
software so we can handle JIC file authorization.

Signed-off-by: Richard Gong <richard.gong@intel.com>
Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c

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intel: common: Remove urgent from mailbox async

Remove urgent argument from asynchrounous mailbox command as any urgent
command should always be synchronous

Signed-off-by: Abdul Halim, Muhammad Had

intel: common: Remove urgent from mailbox async

Remove urgent argument from asynchrounous mailbox command as any urgent
command should always be synchronous

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319

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intel: common: Improve mailbox driver readability

Use pre-defined macros for return values and common mailbox arguments

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdu

intel: common: Improve mailbox driver readability

Use pre-defined macros for return values and common mailbox arguments

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e

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