1 /* 2 * Copyright (c) 2019-2020, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_MBOX_H 8 #define SOCFPGA_MBOX_H 9 10 #include <lib/utils_def.h> 11 12 13 #define MBOX_OFFSET 0xffa30000 14 15 #define MBOX_MAX_JOB_ID 0xf 16 #define MBOX_ATF_CLIENT_ID 0x1 17 #define MBOX_JOB_ID 0x1 18 19 20 /* Mailbox Shared Memory Register Map */ 21 #define MBOX_CIN 0x00 22 #define MBOX_ROUT 0x04 23 #define MBOX_URG 0x08 24 #define MBOX_INT 0x0C 25 #define MBOX_COUT 0x20 26 #define MBOX_RIN 0x24 27 #define MBOX_STATUS 0x2C 28 #define MBOX_CMD_BUFFER 0x40 29 #define MBOX_RESP_BUFFER 0xC0 30 31 /* Mailbox SDM doorbell */ 32 #define MBOX_DOORBELL_TO_SDM 0x400 33 #define MBOX_DOORBELL_FROM_SDM 0x480 34 35 36 /* Mailbox commands */ 37 38 #define MBOX_CMD_NOOP 0x00 39 #define MBOX_CMD_SYNC 0x01 40 #define MBOX_CMD_RESTART 0x02 41 #define MBOX_CMD_CANCEL 0x03 42 #define MBOX_CMD_GET_IDCODE 0x10 43 #define MBOX_CMD_REBOOT_HPS 0x47 44 45 /* Reconfiguration Commands */ 46 #define MBOX_CONFIG_STATUS 0x04 47 #define MBOX_RECONFIG 0x06 48 #define MBOX_RECONFIG_DATA 0x08 49 #define MBOX_RECONFIG_STATUS 0x09 50 51 /* QSPI Commands */ 52 #define MBOX_CMD_QSPI_OPEN 0x32 53 #define MBOX_CMD_QSPI_CLOSE 0x33 54 #define MBOX_CMD_QSPI_SET_CS 0x34 55 #define MBOX_CMD_QSPI_DIRECT 0x3B 56 57 /* RSU Commands */ 58 #define MBOX_GET_SUBPARTITION_TABLE 0x5A 59 #define MBOX_RSU_STATUS 0x5B 60 #define MBOX_RSU_UPDATE 0x5C 61 #define MBOX_HPS_STAGE_NOTIFY 0x5D 62 63 64 /* Mailbox Definitions */ 65 66 #define CMD_DIRECT 0 67 #define CMD_INDIRECT 1 68 #define CMD_CASUAL 0 69 #define CMD_URGENT 1 70 71 #define MBOX_RESP_BUFFER_SIZE 16 72 #define MBOX_CMD_BUFFER_SIZE 32 73 74 /* Execution states for HPS_STAGE_NOTIFY */ 75 #define HPS_EXECUTION_STATE_FSBL 0 76 #define HPS_EXECUTION_STATE_SSBL 1 77 #define HPS_EXECUTION_STATE_OS 2 78 79 /* Status Response */ 80 #define MBOX_RET_OK 0 81 #define MBOX_RET_ERROR -1 82 #define MBOX_NO_RESPONSE -2 83 #define MBOX_WRONG_ID -3 84 #define MBOX_TIMEOUT -2047 85 86 /* Reconfig Status Response */ 87 #define RECONFIG_STATUS_STATE 0 88 #define RECONFIG_STATUS_PIN_STATUS 2 89 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 90 #define PIN_STATUS_NSTATUS (U(1) << 31) 91 #define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) 92 #define SOFTFUNC_STATUS_INIT_DONE (1 << 1) 93 #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) 94 #define MBOX_CFGSTAT_STATE_IDLE 0x00000000 95 #define MBOX_CFGSTAT_STATE_CONFIG 0x10000000 96 #define MBOX_CFGSTAT_STATE_FAILACK 0x08000000 97 #define MBOX_CFGSTAT_STATE_ERROR_INVALID 0xf0000001 98 #define MBOX_CFGSTAT_STATE_ERROR_CORRUPT 0xf0000002 99 #define MBOX_CFGSTAT_STATE_ERROR_AUTH 0xf0000003 100 #define MBOX_CFGSTAT_STATE_ERROR_CORE_IO 0xf0000004 101 #define MBOX_CFGSTAT_STATE_ERROR_HARDWARE 0xf0000005 102 #define MBOX_CFGSTAT_STATE_ERROR_FAKE 0xf0000006 103 #define MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO 0xf0000007 104 #define MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR 0xf0000008 105 106 107 /* Mailbox Macros */ 108 109 /* Mailbox interrupt flags and masks */ 110 #define MBOX_INT_FLAG_COE 0x1 111 #define MBOX_INT_FLAG_RIE 0x2 112 #define MBOX_INT_FLAG_UAE 0x100 113 #define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3) 114 #define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8))) 115 116 /* Mailbox response and status */ 117 #define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x00000fff) 118 #define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12) 119 #define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28) 120 #define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24) 121 #define MBOX_STATUS_UA_MASK (1<<8) 122 123 /* Mailbox command and response */ 124 #define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28) 125 #define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24) 126 #define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12) 127 #define MBOX_INDIRECT(val) ((val) << 11) 128 129 /* RSU Macros */ 130 #define RSU_VERSION_ACMF BIT(8) 131 #define RSU_VERSION_ACMF_MASK 0xff00 132 133 134 /* Mailbox Function Definitions */ 135 136 void mailbox_set_int(int interrupt_input); 137 int mailbox_init(void); 138 void mailbox_set_qspi_close(void); 139 void mailbox_set_qspi_open(void); 140 void mailbox_set_qspi_direct(void); 141 int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args, 142 int len, int urgent, uint32_t *response, int resp_len); 143 int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args, 144 int len, int indirect); 145 int mailbox_read_response(int job_id, uint32_t *response, int resp_len); 146 void mailbox_reset_cold(void); 147 void mailbox_clear_response(void); 148 149 int intel_mailbox_get_config_status(uint32_t cmd); 150 int intel_mailbox_is_fpga_not_ready(void); 151 152 int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len); 153 int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len); 154 int mailbox_rsu_update(uint32_t *flash_offset); 155 int mailbox_hps_stage_notify(uint32_t execution_stage); 156 157 #endif /* SOCFPGA_MBOX_H */ 158