1 /* 2 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_mailbox.h" 14 #include "socfpga_reset_manager.h" 15 #include "socfpga_sip_svc.h" 16 17 /* Number of SiP Calls implemented */ 18 #define SIP_NUM_CALLS 0x3 19 20 /* Total buffer the driver can hold */ 21 #define FPGA_CONFIG_BUFFER_SIZE 4 22 23 static int current_block; 24 static int read_block; 25 static int current_buffer; 26 static int send_id; 27 static int rcv_id; 28 static int max_blocks; 29 static uint32_t bytes_per_block; 30 static uint32_t blocks_submitted; 31 static int is_partial_reconfig; 32 33 struct fpga_config_info { 34 uint32_t addr; 35 int size; 36 int size_written; 37 uint32_t write_requested; 38 int subblocks_sent; 39 int block_number; 40 }; 41 42 /* SiP Service UUID */ 43 DEFINE_SVC_UUID2(intl_svc_uid, 44 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 45 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 46 47 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 48 uint64_t x1, 49 uint64_t x2, 50 uint64_t x3, 51 uint64_t x4, 52 void *cookie, 53 void *handle, 54 uint64_t flags) 55 { 56 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 57 SMC_RET1(handle, SMC_UNK); 58 } 59 60 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 61 62 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 63 { 64 uint32_t args[3]; 65 66 while (max_blocks > 0 && buffer->size > buffer->size_written) { 67 args[0] = (1<<8); 68 args[1] = buffer->addr + buffer->size_written; 69 if (buffer->size - buffer->size_written <= bytes_per_block) { 70 args[2] = buffer->size - buffer->size_written; 71 current_buffer++; 72 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 73 } else 74 args[2] = bytes_per_block; 75 76 buffer->size_written += args[2]; 77 mailbox_send_cmd_async(send_id++ % MBOX_MAX_JOB_ID, 78 MBOX_RECONFIG_DATA, args, 3, 79 CMD_INDIRECT); 80 81 buffer->subblocks_sent++; 82 max_blocks--; 83 } 84 85 return !max_blocks; 86 } 87 88 static int intel_fpga_sdm_write_all(void) 89 { 90 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 91 if (intel_fpga_sdm_write_buffer( 92 &fpga_config_buffers[current_buffer])) 93 break; 94 return 0; 95 } 96 97 static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) 98 { 99 uint32_t ret; 100 101 if (query_type == 1) 102 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS); 103 else 104 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS); 105 106 if (ret) { 107 if (ret == MBOX_CFGSTAT_STATE_CONFIG) 108 return INTEL_SIP_SMC_STATUS_BUSY; 109 else 110 return INTEL_SIP_SMC_STATUS_ERROR; 111 } 112 113 if (query_type != 1) { 114 /* full reconfiguration */ 115 if (!is_partial_reconfig) 116 socfpga_bridges_enable(); /* Enable bridge */ 117 } 118 119 return INTEL_SIP_SMC_STATUS_OK; 120 } 121 122 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 123 { 124 int i; 125 126 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 127 if (fpga_config_buffers[i].block_number == current_block) { 128 fpga_config_buffers[i].subblocks_sent--; 129 if (fpga_config_buffers[i].subblocks_sent == 0 130 && fpga_config_buffers[i].size <= 131 fpga_config_buffers[i].size_written) { 132 fpga_config_buffers[i].write_requested = 0; 133 current_block++; 134 *buffer_addr_completed = 135 fpga_config_buffers[i].addr; 136 return 0; 137 } 138 } 139 } 140 141 return -1; 142 } 143 144 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 145 uint32_t *count) 146 { 147 uint32_t status = INTEL_SIP_SMC_STATUS_OK; 148 *count = 0; 149 int resp_len = 0; 150 uint32_t resp[5]; 151 int all_completed = 1; 152 153 while (*count < 3) { 154 155 resp_len = mailbox_read_response(rcv_id % MBOX_MAX_JOB_ID, 156 resp, ARRAY_SIZE(resp)); 157 158 if (resp_len < 0) 159 break; 160 161 max_blocks++; 162 rcv_id++; 163 164 if (mark_last_buffer_xfer_completed( 165 &completed_addr[*count]) == 0) 166 *count = *count + 1; 167 else 168 break; 169 } 170 171 if (*count <= 0) { 172 if (resp_len != MBOX_NO_RESPONSE && 173 resp_len != MBOX_TIMEOUT && resp_len != 0) { 174 mailbox_clear_response(); 175 return INTEL_SIP_SMC_STATUS_ERROR; 176 } 177 178 *count = 0; 179 } 180 181 intel_fpga_sdm_write_all(); 182 183 if (*count > 0) 184 status = INTEL_SIP_SMC_STATUS_OK; 185 else if (*count == 0) 186 status = INTEL_SIP_SMC_STATUS_BUSY; 187 188 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 189 if (fpga_config_buffers[i].write_requested != 0) { 190 all_completed = 0; 191 break; 192 } 193 } 194 195 if (all_completed == 1) 196 return INTEL_SIP_SMC_STATUS_OK; 197 198 return status; 199 } 200 201 static int intel_fpga_config_start(uint32_t config_type) 202 { 203 uint32_t response[3]; 204 int status = 0; 205 206 is_partial_reconfig = config_type; 207 208 mailbox_clear_response(); 209 210 mailbox_send_cmd(1, MBOX_CMD_CANCEL, NULL, 0, CMD_CASUAL, NULL, 0); 211 212 status = mailbox_send_cmd(1, MBOX_RECONFIG, NULL, 0, CMD_CASUAL, 213 response, ARRAY_SIZE(response)); 214 215 if (status < 0) 216 return status; 217 218 max_blocks = response[0]; 219 bytes_per_block = response[1]; 220 221 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 222 fpga_config_buffers[i].size = 0; 223 fpga_config_buffers[i].size_written = 0; 224 fpga_config_buffers[i].addr = 0; 225 fpga_config_buffers[i].write_requested = 0; 226 fpga_config_buffers[i].block_number = 0; 227 fpga_config_buffers[i].subblocks_sent = 0; 228 } 229 230 blocks_submitted = 0; 231 current_block = 0; 232 read_block = 0; 233 current_buffer = 0; 234 send_id = 0; 235 rcv_id = 0; 236 237 /* full reconfiguration */ 238 if (!is_partial_reconfig) { 239 /* Disable bridge */ 240 socfpga_bridges_disable(); 241 } 242 243 return 0; 244 } 245 246 static bool is_fpga_config_buffer_full(void) 247 { 248 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) 249 if (!fpga_config_buffers[i].write_requested) 250 return false; 251 return true; 252 } 253 254 static bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 255 { 256 if (size > (UINT64_MAX - addr)) 257 return false; 258 if (addr < BL31_LIMIT) 259 return false; 260 if (addr + size > DRAM_BASE + DRAM_SIZE) 261 return false; 262 263 return true; 264 } 265 266 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 267 { 268 int i; 269 270 intel_fpga_sdm_write_all(); 271 272 if (!is_address_in_ddr_range(mem, size) || 273 is_fpga_config_buffer_full()) 274 return INTEL_SIP_SMC_STATUS_REJECTED; 275 276 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 277 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 278 279 if (!fpga_config_buffers[j].write_requested) { 280 fpga_config_buffers[j].addr = mem; 281 fpga_config_buffers[j].size = size; 282 fpga_config_buffers[j].size_written = 0; 283 fpga_config_buffers[j].write_requested = 1; 284 fpga_config_buffers[j].block_number = 285 blocks_submitted++; 286 fpga_config_buffers[j].subblocks_sent = 0; 287 break; 288 } 289 } 290 291 if (is_fpga_config_buffer_full()) 292 return INTEL_SIP_SMC_STATUS_BUSY; 293 294 return INTEL_SIP_SMC_STATUS_OK; 295 } 296 297 static int is_out_of_sec_range(uint64_t reg_addr) 298 { 299 switch (reg_addr) { 300 case(0xF8011100): /* ECCCTRL1 */ 301 case(0xF8011104): /* ECCCTRL2 */ 302 case(0xF8011110): /* ERRINTEN */ 303 case(0xF8011114): /* ERRINTENS */ 304 case(0xF8011118): /* ERRINTENR */ 305 case(0xF801111C): /* INTMODE */ 306 case(0xF8011120): /* INTSTAT */ 307 case(0xF8011124): /* DIAGINTTEST */ 308 case(0xF801112C): /* DERRADDRA */ 309 case(0xFFD12028): /* SDMMCGRP_CTRL */ 310 case(0xFFD12044): /* EMAC0 */ 311 case(0xFFD12048): /* EMAC1 */ 312 case(0xFFD1204C): /* EMAC2 */ 313 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 314 case(0xFFD12094): /* ECC_INT_MASK_SET */ 315 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 316 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 317 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 318 case(0xFFD120C0): /* NOC_TIMEOUT */ 319 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 320 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 321 case(0xFFD120D0): /* NOC_IDLEACK */ 322 case(0xFFD120D4): /* NOC_IDLESTATUS */ 323 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 324 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 325 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 326 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 327 return 0; 328 329 default: 330 break; 331 } 332 333 return -1; 334 } 335 336 /* Secure register access */ 337 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 338 { 339 if (is_out_of_sec_range(reg_addr)) 340 return INTEL_SIP_SMC_STATUS_ERROR; 341 342 *retval = mmio_read_32(reg_addr); 343 344 return INTEL_SIP_SMC_STATUS_OK; 345 } 346 347 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 348 uint32_t *retval) 349 { 350 if (is_out_of_sec_range(reg_addr)) 351 return INTEL_SIP_SMC_STATUS_ERROR; 352 353 mmio_write_32(reg_addr, val); 354 355 return intel_secure_reg_read(reg_addr, retval); 356 } 357 358 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 359 uint32_t val, uint32_t *retval) 360 { 361 if (!intel_secure_reg_read(reg_addr, retval)) { 362 *retval &= ~mask; 363 *retval |= val; 364 return intel_secure_reg_write(reg_addr, *retval, retval); 365 } 366 367 return INTEL_SIP_SMC_STATUS_ERROR; 368 } 369 370 /* Intel Remote System Update (RSU) services */ 371 uint64_t intel_rsu_update_address; 372 373 static uint32_t intel_rsu_status(uint64_t *respbuf, uint32_t respbuf_sz) 374 { 375 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 376 return INTEL_SIP_SMC_RSU_ERROR; 377 378 return INTEL_SIP_SMC_STATUS_OK; 379 } 380 381 static uint32_t intel_rsu_update(uint64_t update_address) 382 { 383 intel_rsu_update_address = update_address; 384 return INTEL_SIP_SMC_STATUS_OK; 385 } 386 387 static uint32_t intel_rsu_notify(uint32_t execution_stage) 388 { 389 if (mailbox_hps_stage_notify(execution_stage) < 0) 390 return INTEL_SIP_SMC_RSU_ERROR; 391 392 return INTEL_SIP_SMC_STATUS_OK; 393 } 394 395 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 396 uint32_t *ret_stat) 397 { 398 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) 399 return INTEL_SIP_SMC_RSU_ERROR; 400 401 *ret_stat = respbuf[8]; 402 return INTEL_SIP_SMC_STATUS_OK; 403 } 404 405 /* Mailbox services */ 406 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, int len, 407 int urgent, uint32_t *response, 408 int resp_len, int *mbox_status, 409 int *len_in_resp) 410 { 411 *len_in_resp = 0; 412 *mbox_status = 0; 413 414 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) 415 return INTEL_SIP_SMC_STATUS_REJECTED; 416 417 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 418 response, resp_len); 419 420 if (status < 0) { 421 *mbox_status = -status; 422 return INTEL_SIP_SMC_STATUS_ERROR; 423 } 424 425 *mbox_status = 0; 426 *len_in_resp = status; 427 return INTEL_SIP_SMC_STATUS_OK; 428 } 429 430 /* 431 * This function is responsible for handling all SiP calls from the NS world 432 */ 433 434 uintptr_t sip_smc_handler(uint32_t smc_fid, 435 u_register_t x1, 436 u_register_t x2, 437 u_register_t x3, 438 u_register_t x4, 439 void *cookie, 440 void *handle, 441 u_register_t flags) 442 { 443 uint32_t val = 0; 444 uint32_t status = INTEL_SIP_SMC_STATUS_OK; 445 uint32_t completed_addr[3]; 446 uint64_t rsu_respbuf[9]; 447 uint32_t count = 0; 448 u_register_t x5, x6; 449 int mbox_status, len_in_resp; 450 451 452 switch (smc_fid) { 453 case SIP_SVC_UID: 454 /* Return UID to the caller */ 455 SMC_UUID_RET(handle, intl_svc_uid); 456 457 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 458 status = intel_mailbox_fpga_config_isdone(x1); 459 SMC_RET4(handle, status, 0, 0, 0); 460 461 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 462 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 463 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 464 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 465 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 466 467 case INTEL_SIP_SMC_FPGA_CONFIG_START: 468 status = intel_fpga_config_start(x1); 469 SMC_RET4(handle, status, 0, 0, 0); 470 471 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 472 status = intel_fpga_config_write(x1, x2); 473 SMC_RET4(handle, status, 0, 0, 0); 474 475 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 476 status = intel_fpga_config_completed_write(completed_addr, 477 &count); 478 switch (count) { 479 case 1: 480 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 481 completed_addr[0], 0, 0); 482 483 case 2: 484 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 485 completed_addr[0], 486 completed_addr[1], 0); 487 488 case 3: 489 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 490 completed_addr[0], 491 completed_addr[1], 492 completed_addr[2]); 493 494 case 0: 495 SMC_RET4(handle, status, 0, 0, 0); 496 497 default: 498 mailbox_clear_response(); 499 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 500 } 501 502 case INTEL_SIP_SMC_REG_READ: 503 status = intel_secure_reg_read(x1, &val); 504 SMC_RET3(handle, status, val, x1); 505 506 case INTEL_SIP_SMC_REG_WRITE: 507 status = intel_secure_reg_write(x1, (uint32_t)x2, &val); 508 SMC_RET3(handle, status, val, x1); 509 510 case INTEL_SIP_SMC_REG_UPDATE: 511 status = intel_secure_reg_update(x1, (uint32_t)x2, 512 (uint32_t)x3, &val); 513 SMC_RET3(handle, status, val, x1); 514 515 case INTEL_SIP_SMC_RSU_STATUS: 516 status = intel_rsu_status(rsu_respbuf, 517 ARRAY_SIZE(rsu_respbuf)); 518 if (status) { 519 SMC_RET1(handle, status); 520 } else { 521 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 522 rsu_respbuf[2], rsu_respbuf[3]); 523 } 524 525 case INTEL_SIP_SMC_RSU_UPDATE: 526 status = intel_rsu_update(x1); 527 SMC_RET1(handle, status); 528 529 case INTEL_SIP_SMC_RSU_NOTIFY: 530 status = intel_rsu_notify(x1); 531 SMC_RET1(handle, status); 532 533 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 534 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 535 ARRAY_SIZE(rsu_respbuf), &val); 536 if (status) { 537 SMC_RET1(handle, status); 538 } else { 539 SMC_RET2(handle, status, val); 540 } 541 542 case INTEL_SIP_SMC_MBOX_SEND_CMD: 543 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 544 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 545 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, 546 (uint32_t *)x5, x6, &mbox_status, 547 &len_in_resp); 548 SMC_RET4(handle, status, mbox_status, x5, len_in_resp); 549 550 default: 551 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 552 cookie, handle, flags); 553 } 554 } 555 556 DECLARE_RT_SVC( 557 socfpga_sip_svc, 558 OEN_SIP_START, 559 OEN_SIP_END, 560 SMC_TYPE_FAST, 561 NULL, 562 sip_smc_handler 563 ); 564 565 DECLARE_RT_SVC( 566 socfpga_sip_svc_std, 567 OEN_SIP_START, 568 OEN_SIP_END, 569 SMC_TYPE_YIELD, 570 NULL, 571 sip_smc_handler 572 ); 573