feat(plat/mediatek/mt8195): add support for PTP3

Add PTP3 drivers to protect CPU excessive voltage drop
in CPU heavy loading.

Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d
Signed-off-by: Ell

feat(plat/mediatek/mt8195): add support for PTP3

Add PTP3 drivers to protect CPU excessive voltage drop
in CPU heavy loading.

Change-Id: I7bd37912c32d5328ba0287fccc8409794bd19c1d
Signed-off-by: Elly Chiang <elly.chiang@mediatek.com>

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fix(plat/mediatek/mt8195): extend MMU region size

In mt8195 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn

fix(plat/mediatek/mt8195): extend MMU region size

In mt8195 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.

This patch extends the MMU region 0 size to cover all mt8195 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.

Change-Id: I3a186ed71d0d963b59ae55e27a6d27a01fe4f638
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>

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feat(spm): add Ivy partition to tb fw config

The partition layout description JSON file generated by TF-A tests
declares a fourth test partition called Ivy demonstrating the
implementation of a S-EL

feat(spm): add Ivy partition to tb fw config

The partition layout description JSON file generated by TF-A tests
declares a fourth test partition called Ivy demonstrating the
implementation of a S-EL0 partition supported by a S-EL1 shim.

Change-Id: If8562acfc045d6496dfdb3df0524b3a069357f8e
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>

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Merge changes from topic "st_fixes" into integration

* changes:
fix(plat/st): correct IO compensation disabling
fix(plat/st): correct BSEC error code management
fix(drivers/st/pmic): missing e

Merge changes from topic "st_fixes" into integration

* changes:
fix(plat/st): correct IO compensation disabling
fix(plat/st): correct BSEC error code management
fix(drivers/st/pmic): missing error check
fix(drivers/st/pmic): initialize i2c_state
fix(drivers/st/clk): use correct return value

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refactor(plat/st): add stm32image_io_setup

Add a generic function to setup the stm32image IO.

Change-Id: I0f7cf4a6030605037643f3119b809e0319d926af
Signed-off-by: Patrick Delaunay <patrick.delaunay@

refactor(plat/st): add stm32image_io_setup

Add a generic function to setup the stm32image IO.

Change-Id: I0f7cf4a6030605037643f3119b809e0319d926af
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(plat/st): panic if boot interface is wrong

Add a panic() at the end of stm32mp_io_setup() if the boot interface
given in ROM code boot context is not supported.

Change-Id: I0d50f21a11231febd210

fix(plat/st): panic if boot interface is wrong

Add a panic() at the end of stm32mp_io_setup() if the boot interface
given in ROM code boot context is not supported.

Change-Id: I0d50f21a11231febd21041b6e63108cc3e6f4f0c
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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Merge "feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1" into integration

Merge changes from topic "tc0_tfa_v25" into integration

* changes:
fix(tc0): remove ffa and optee device tree node
fix(tc0): set cactus-tertiary vcpu count to 1
fix(tc0): change UUID to string

Merge changes from topic "tc0_tfa_v25" into integration

* changes:
fix(tc0): remove ffa and optee device tree node
fix(tc0): set cactus-tertiary vcpu count to 1
fix(tc0): change UUID to string format

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refactor(plat/fvp): tidy up list of images to measure

We don't ever expect to load a binary with an STM32 header on the Arm
FVP platform so remove this type of image from the list of
measurements.

refactor(plat/fvp): tidy up list of images to measure

We don't ever expect to load a binary with an STM32 header on the Arm
FVP platform so remove this type of image from the list of
measurements.

Also remove the GPT image type from the list, as it does not get
measured. GPT is a container, just like FIP is. We don't measure the FIP
but rather the images inside it. It would seem logical to treat GPT the
same way.

Besides, only images that get loaded through load_auth_image() get
measured right now. GPT processing happens before that and is handled in
a different way (see partition_init()).

Change-Id: Iac4de75380ed625b228e69ee4564cf9e67e19336
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1

For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The un

feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1

For Arm platforms PIE is enabled when RESET_TO_BL31=1 in aarch64 mode on
the similar lines enable PIE when RESET_TO_SP_MIN=1 in aarch32 mode.
The underlying changes for enabling PIE in aarch32 is submitted in
commit 4324a14bf

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib8bb860198b3f97cdc91005503a3184d63e15469

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fix(tc0): set cactus-tertiary vcpu count to 1

Third instance of cactus is a UP SP. Set its vcpu count to 1.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I34b7feb2

fix(tc0): set cactus-tertiary vcpu count to 1

Third instance of cactus is a UP SP. Set its vcpu count to 1.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I34b7feb2915e6d335e690e89dea466e75944ed1b

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fix(tc0): change UUID to string format

Change OP-TEE, Cactus SPs UUID to string format

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I32dbf40e4c5aa959bb92d3e853072

fix(tc0): change UUID to string format

Change OP-TEE, Cactus SPs UUID to string format

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I32dbf40e4c5aa959bb92d3e853072aea63409ddc

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refactor(plat/nxp/lx216x): refine variable definition

This patch will make BL2_BASE to be hex valaue but
not a shell command.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iebb86a0b9bc8

refactor(plat/nxp/lx216x): refine variable definition

This patch will make BL2_BASE to be hex valaue but
not a shell command.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Iebb86a0b9bc8cab1676bd8e898cf4a1b6d16f472

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refactor(plat/nxp/lx216x): use common make variables

Some build variables have already defined in common
make helper file, use them directly.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-I

refactor(plat/nxp/lx216x): use common make variables

Some build variables have already defined in common
make helper file, use them directly.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I7fe6331160bfdf315924d4498d78b0a399eb2e89

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fix(rockchip/rk3399): fix dram section placement

To quote jwerner in T925:
"The __sramdata in the declaration is a mistake, the correct target
section for that global needs to be .pmusram.data. This

fix(rockchip/rk3399): fix dram section placement

To quote jwerner in T925:
"The __sramdata in the declaration is a mistake, the correct target
section for that global needs to be .pmusram.data. This used to be
in .sram.data once upon a time but then the suspend.c stuff got added
and required it to be moved to PMUSRAM. I guess they forgot to update
that part in the declaration and since the old GCC seemed to silently
prefer the attribute in the definition, nobody noticed."

This fixes building with gcc 11.

fix #T925

Change-Id: I2b91542277c95cf487eaa1344927294d5d1b8f2b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>

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fix(plat/st): correct IO compensation disabling

In stm32mp1_syscfg_disable_io_compensation(), to disable the IO
compensation cell, we have to set the corresponding bit in
SYSCFG_CMPENCLRR register,

fix(plat/st): correct IO compensation disabling

In stm32mp1_syscfg_disable_io_compensation(), to disable the IO
compensation cell, we have to set the corresponding bit in
SYSCFG_CMPENCLRR register, instead of clearing the bit in SETR register.

Change-Id: I510a50451f8afb9e98c24e1ea84efbf73a39e6b4
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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fix(plat/st): add STM32IMAGE_SRC

The dependency on this macro was added by patch [1]. But the macro
itself was forgotten in the patch.

[1] 128e0b3e2e0 ("stm32mp1: update rules for stm32image tool"

fix(plat/st): add STM32IMAGE_SRC

The dependency on this macro was added by patch [1]. But the macro
itself was forgotten in the patch.

[1] 128e0b3e2e0 ("stm32mp1: update rules for stm32image tool")

Change-Id: I49219e1e13828b97b95f404983da33ef4567fe23
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(plat/st): correct BSEC error code management

BSEC services should return SMC error codes as other IDs (defined in
stm32mp1_smc.h) and not BSEC driver ones. So that non-secure caller
is able to t

fix(plat/st): correct BSEC error code management

BSEC services should return SMC error codes as other IDs (defined in
stm32mp1_smc.h) and not BSEC driver ones. So that non-secure caller
is able to treat them correctly.

In global SMC handler, unknown ID should also return a value from this
definition list, and not the generic one, which seems not well adapted
for our needs.

Two unsigned values initializations are also changed from 0 to 0U.

Change-Id: Ib6fd3866a748cefad1d13d48f7be38241621023e
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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Merge changes from topic "imx8m-sdei" into integration

* changes:
feat(plat/imx8m): add sdei support for i.MX8MP
feat(plat/imx8m): add sdei support for i.MX8MN

Merge "refactor(plat/zynqmp): optimize the code to save some space" into integration

Merge "refactor(plat/st): check boot device only for BL2" into integration

Merge "feat(plat/imx8m): add system_reset2 implementation" into integration

refactor(plat/zynqmp): optimize the code to save some space

As there is constraint with the space for the release builds,
remove some of the legacy code.

Signed-off-by: Venkatesh Yadav Abbarapu <ve

refactor(plat/zynqmp): optimize the code to save some space

As there is constraint with the space for the release builds,
remove some of the legacy code.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I5b8b16f34ed8e480f16ab1aeac80b85cdb391852

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feat(plat/imx8m): add system_reset2 implementation

Add imx_system_reset2 which extends existing SYSTEM_RESET. It provides
architectural reset definitions and vendor-specific resets.
By default warm

feat(plat/imx8m): add system_reset2 implementation

Add imx_system_reset2 which extends existing SYSTEM_RESET. It provides
architectural reset definitions and vendor-specific resets.
By default warm reset is triggered.

Also refactor existing implementation of wdog reset, add details about
each flag used.

Change-Id: Ia7348c32c385f1c61f8085776e81dd1e38ddda5c
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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Merge "refactor(plat/st): avoid fixed DT address" into integration