1 /* 2 * Copyright (c) 2021, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* common headers */ 8 #include <assert.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/gpio.h> 13 #include <lib/psci/psci.h> 14 15 /* platform specific headers */ 16 #include <mt_gic_v3.h> 17 #include <mtk_ptp3_common.h> 18 #include <mtspmc.h> 19 #include <plat/common/platform.h> 20 #include <plat_mtk_lpm.h> 21 #include <plat_params.h> 22 #include <plat_pm.h> 23 #include <pmic.h> 24 #include <rtc.h> 25 26 /* 27 * Cluster state request: 28 * [0] : The CPU requires cluster power down 29 * [1] : The CPU requires cluster power on 30 */ 31 #define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff) 32 #define coordinate_cluster_pwron() coordinate_cluster(1) 33 #define coordinate_cluster_pwroff() coordinate_cluster(0) 34 35 /* platform secure entry point */ 36 static uintptr_t secure_entrypoint; 37 /* per-CPU power state */ 38 static unsigned int plat_power_state[PLATFORM_CORE_COUNT]; 39 40 /* platform CPU power domain - ops */ 41 static const struct mt_lpm_tz *plat_mt_pm; 42 43 #define plat_mt_pm_invoke(_name, _cpu, _state) ({ \ 44 int ret = -1; \ 45 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ 46 ret = plat_mt_pm->_name(_cpu, _state); \ 47 } \ 48 ret; }) 49 50 #define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \ 51 if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \ 52 (void) plat_mt_pm->_name(_cpu, _state); \ 53 } \ 54 }) 55 56 /* 57 * Common MTK_platform operations to power on/off a 58 * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 59 */ 60 61 static void plat_cpu_pwrdwn_common(unsigned int cpu, 62 const psci_power_state_t *state, unsigned int req_pstate) 63 { 64 assert(cpu == plat_my_core_pos()); 65 66 plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state); 67 68 if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) || 69 (req_pstate == 0U)) { /* hotplug off */ 70 coordinate_cluster_pwroff(); 71 } 72 73 /* Prevent interrupts from spuriously waking up this CPU */ 74 mt_gic_rdistif_save(); 75 gicv3_cpuif_disable(cpu); 76 gicv3_rdistif_off(cpu); 77 } 78 79 static void plat_cpu_pwron_common(unsigned int cpu, 80 const psci_power_state_t *state, unsigned int req_pstate) 81 { 82 assert(cpu == plat_my_core_pos()); 83 84 plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state); 85 86 coordinate_cluster_pwron(); 87 88 /* PTP3 config */ 89 ptp3_core_init(cpu); 90 91 /* Enable the GIC CPU interface */ 92 gicv3_rdistif_on(cpu); 93 gicv3_cpuif_enable(cpu); 94 mt_gic_rdistif_init(); 95 96 /* 97 * If mcusys does power down before then restore 98 * all CPUs' GIC Redistributors 99 */ 100 if (IS_MCUSYS_OFF_STATE(state)) { 101 mt_gic_rdistif_restore_all(); 102 } else { 103 mt_gic_rdistif_restore(); 104 } 105 } 106 107 /* 108 * Common MTK_platform operations to power on/off a 109 * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 110 */ 111 112 static void plat_cluster_pwrdwn_common(unsigned int cpu, 113 const psci_power_state_t *state, unsigned int req_pstate) 114 { 115 assert(cpu == plat_my_core_pos()); 116 117 if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) { 118 coordinate_cluster_pwron(); 119 120 /* TODO: return on fail. 121 * Add a 'return' here before adding any code following 122 * the if-block. 123 */ 124 } 125 } 126 127 static void plat_cluster_pwron_common(unsigned int cpu, 128 const psci_power_state_t *state, unsigned int req_pstate) 129 { 130 assert(cpu == plat_my_core_pos()); 131 132 if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) { 133 /* TODO: return on fail. 134 * Add a 'return' here before adding any code following 135 * the if-block. 136 */ 137 } 138 } 139 140 /* 141 * Common MTK_platform operations to power on/off a 142 * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request. 143 */ 144 145 static void plat_mcusys_pwrdwn_common(unsigned int cpu, 146 const psci_power_state_t *state, unsigned int req_pstate) 147 { 148 assert(cpu == plat_my_core_pos()); 149 150 if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) { 151 return; /* return on fail */ 152 } 153 154 mt_gic_distif_save(); 155 gic_sgi_save_all(); 156 } 157 158 static void plat_mcusys_pwron_common(unsigned int cpu, 159 const psci_power_state_t *state, unsigned int req_pstate) 160 { 161 assert(cpu == plat_my_core_pos()); 162 163 if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) { 164 return; /* return on fail */ 165 } 166 167 mt_gic_init(); 168 mt_gic_distif_restore(); 169 gic_sgi_restore_all(); 170 171 plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state); 172 } 173 174 /* 175 * plat_psci_ops implementation 176 */ 177 178 static void plat_cpu_standby(plat_local_state_t cpu_state) 179 { 180 uint64_t scr; 181 182 scr = read_scr_el3(); 183 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 184 185 isb(); 186 dsb(); 187 wfi(); 188 189 write_scr_el3(scr); 190 } 191 192 static int plat_power_domain_on(u_register_t mpidr) 193 { 194 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 195 unsigned int cluster = 0U; 196 197 if (cpu >= PLATFORM_CORE_COUNT) { 198 return PSCI_E_INVALID_PARAMS; 199 } 200 201 if (!spm_get_cluster_powerstate(cluster)) { 202 spm_poweron_cluster(cluster); 203 } 204 205 /* init CPU reset arch as AARCH64 */ 206 mcucfg_init_archstate(cluster, cpu, true); 207 mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint); 208 spm_poweron_cpu(cluster, cpu); 209 210 return PSCI_E_SUCCESS; 211 } 212 213 static void plat_power_domain_on_finish(const psci_power_state_t *state) 214 { 215 unsigned long mpidr = read_mpidr_el1(); 216 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 217 218 assert(cpu < PLATFORM_CORE_COUNT); 219 220 /* Allow IRQs to wakeup this core in IDLE flow */ 221 mcucfg_enable_gic_wakeup(0U, cpu); 222 223 if (IS_CLUSTER_OFF_STATE(state)) { 224 plat_cluster_pwron_common(cpu, state, 0U); 225 } 226 227 plat_cpu_pwron_common(cpu, state, 0U); 228 } 229 230 static void plat_power_domain_off(const psci_power_state_t *state) 231 { 232 unsigned long mpidr = read_mpidr_el1(); 233 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr); 234 235 assert(cpu < PLATFORM_CORE_COUNT); 236 237 plat_cpu_pwrdwn_common(cpu, state, 0U); 238 spm_poweroff_cpu(0U, cpu); 239 240 /* prevent unintended IRQs from waking up the hot-unplugged core */ 241 mcucfg_disable_gic_wakeup(0U, cpu); 242 243 if (IS_CLUSTER_OFF_STATE(state)) { 244 plat_cluster_pwrdwn_common(cpu, state, 0U); 245 } 246 } 247 248 static void plat_power_domain_suspend(const psci_power_state_t *state) 249 { 250 unsigned int cpu = plat_my_core_pos(); 251 252 assert(cpu < PLATFORM_CORE_COUNT); 253 254 plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state); 255 256 /* Perform the common CPU specific operations */ 257 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]); 258 259 if (IS_CLUSTER_OFF_STATE(state)) { 260 /* Perform the common cluster specific operations */ 261 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]); 262 } 263 264 if (IS_MCUSYS_OFF_STATE(state)) { 265 /* Perform the common mcusys specific operations */ 266 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]); 267 } 268 } 269 270 static void plat_power_domain_suspend_finish(const psci_power_state_t *state) 271 { 272 unsigned int cpu = plat_my_core_pos(); 273 274 assert(cpu < PLATFORM_CORE_COUNT); 275 276 if (IS_MCUSYS_OFF_STATE(state)) { 277 /* Perform the common mcusys specific operations */ 278 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]); 279 } 280 281 if (IS_CLUSTER_OFF_STATE(state)) { 282 /* Perform the common cluster specific operations */ 283 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]); 284 } 285 286 /* Perform the common CPU specific operations */ 287 plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]); 288 289 plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state); 290 } 291 292 static int plat_validate_power_state(unsigned int power_state, 293 psci_power_state_t *req_state) 294 { 295 unsigned int pstate = psci_get_pstate_type(power_state); 296 unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state); 297 unsigned int cpu = plat_my_core_pos(); 298 299 if (aff_lvl > PLAT_MAX_PWR_LVL) { 300 return PSCI_E_INVALID_PARAMS; 301 } 302 303 if (pstate == PSTATE_TYPE_STANDBY) { 304 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE; 305 } else { 306 unsigned int i; 307 unsigned int pstate_id = psci_get_pstate_id(power_state); 308 plat_local_state_t s = MTK_LOCAL_STATE_OFF; 309 310 /* Use pstate_id to be power domain state */ 311 if (pstate_id > s) { 312 s = (plat_local_state_t)pstate_id; 313 } 314 315 for (i = 0U; i <= aff_lvl; i++) { 316 req_state->pwr_domain_state[i] = s; 317 } 318 } 319 320 plat_power_state[cpu] = power_state; 321 return PSCI_E_SUCCESS; 322 } 323 324 static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state) 325 { 326 unsigned int lv; 327 unsigned int cpu = plat_my_core_pos(); 328 329 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { 330 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE; 331 } 332 333 plat_power_state[cpu] = 334 psci_make_powerstate( 335 MT_PLAT_PWR_STATE_SYSTEM_SUSPEND, 336 PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL); 337 338 flush_dcache_range((uintptr_t) 339 &plat_power_state[cpu], 340 sizeof(plat_power_state[cpu])); 341 } 342 343 /******************************************************************************* 344 * MTK handlers to shutdown/reboot the system 345 ******************************************************************************/ 346 static void __dead2 plat_mtk_system_reset(void) 347 { 348 struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset(); 349 350 INFO("MTK System Reset\n"); 351 352 gpio_set_value(gpio_reset->index, gpio_reset->polarity); 353 354 wfi(); 355 ERROR("MTK System Reset: operation not handled.\n"); 356 panic(); 357 } 358 359 static void __dead2 plat_mtk_system_off(void) 360 { 361 INFO("MTK System Off\n"); 362 363 rtc_power_off_sequence(); 364 pmic_power_off(); 365 366 wfi(); 367 ERROR("MTK System Off: operation not handled.\n"); 368 panic(); 369 } 370 371 static const plat_psci_ops_t plat_psci_ops = { 372 .system_reset = plat_mtk_system_reset, 373 .system_off = plat_mtk_system_off, 374 .cpu_standby = plat_cpu_standby, 375 .pwr_domain_on = plat_power_domain_on, 376 .pwr_domain_on_finish = plat_power_domain_on_finish, 377 .pwr_domain_off = plat_power_domain_off, 378 .pwr_domain_suspend = plat_power_domain_suspend, 379 .pwr_domain_suspend_finish = plat_power_domain_suspend_finish, 380 .validate_power_state = plat_validate_power_state, 381 .get_sys_suspend_power_state = plat_get_sys_suspend_power_state 382 }; 383 384 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 385 const plat_psci_ops_t **psci_ops) 386 { 387 *psci_ops = &plat_psci_ops; 388 secure_entrypoint = sec_entrypoint; 389 390 /* 391 * init the warm reset config for boot CPU 392 * reset arch as AARCH64 393 * reset addr as function bl31_warm_entrypoint() 394 */ 395 mcucfg_init_archstate(0U, 0U, true); 396 mcucfg_set_bootaddr(0U, 0U, secure_entrypoint); 397 398 spmc_init(); 399 plat_mt_pm = mt_plat_cpu_pm_init(); 400 401 return 0; 402 } 403