fix(plat/mediatek/me8195): fix error setting for SPM

There is a error setting for SPM, so we need to fix this issue.

Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a

fix(plat/mediatek/me8195): fix error setting for SPM

There is a error setting for SPM, so we need to fix this issue.

Signed-off-by: Garmin Chang <garmin.chang@mediatek.com>
Change-Id: I741a5dc1505a831fe48fd5bc3da9904db14c8a57

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fix(rk3399/suspend): correct LPDDR4 resume sequence

This change adds 208 bytes to PMUSRAM, pushing the end of text from
0xff3b0de0 to 0xff3b0eb0, which is still shy of the maximum
0xff3b1000.

Furth

fix(rk3399/suspend): correct LPDDR4 resume sequence

This change adds 208 bytes to PMUSRAM, pushing the end of text from
0xff3b0de0 to 0xff3b0eb0, which is still shy of the maximum
0xff3b1000.

Further, this skips enabling the watchdog when it's not being used
elsewhere, as you can't turn the watchdog off.

Change-Id: I2e6fa3c7e01f2be6b32ce04ce479edf64e278554
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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Merge changes Iebb86a0b,I7fe63311 into integration

* changes:
refactor(plat/nxp/lx216x): refine variable definition
refactor(plat/nxp/lx216x): use common make variables

Merge changes I2b3aa9bd,I3237199b into integration

* changes:
docs: add mt6795 to deprecated list
feat(plat/mediatek/mt8195): add DCM driver

Merge "fix(plat/marvell/a3k): fix printing info messages on output" into integration

Merge "fix(rockchip/rk3399): fix dram section placement" into integration

fix(plat/marvell/a3k): fix printing info messages on output

INFO() macro for every call prepends "INFO: " string. Therefore
current code prints unreadable debug messages:

"INFO: set_io_add

fix(plat/marvell/a3k): fix printing info messages on output

INFO() macro for every call prepends "INFO: " string. Therefore
current code prints unreadable debug messages:

"INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0)INFO: "
"INFO: Set IO decode window successfully, base(0xc000)INFO: win_attr(3d) max_dram_win(2) max_remap(0)INFO: win_offset(8)"

Fix it by calling exactly one INFO() call for one line. After this
change output is:

"INFO: set_io_addr_dec 0 result: ctrl(0x3fff3d01) base(0x0) remap(0x0)"
"INFO: Set IO decode window successfully, base(0xc000) win_attr(3d) max_dram_win(2) max_remap(0) win_offset(8)"

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6084e64c6f4da6c1929e5300588e4ba2608ca745

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feat(plat/st): add helper to save boot interface

Some parameters from BootROM boot context can be required after boot.
To save space in SYSRAM, this context can be overwritten during images
load seq

feat(plat/st): add helper to save boot interface

Some parameters from BootROM boot context can be required after boot.
To save space in SYSRAM, this context can be overwritten during images
load sequence. The needed information (here the boot interface) is
then saved in a local variable.

Change-Id: I5e1ad4630ccf78480f415a0a83939005ae67729e
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(plat/st): improve DDR get size function

Avoid parsing device tree every time when returning
the DDR size.
A cache flush on this size is also added because TZC400 configuration
is applied at the

fix(plat/st): improve DDR get size function

Avoid parsing device tree every time when returning
the DDR size.
A cache flush on this size is also added because TZC400 configuration
is applied at the end of BL2 after MMU and data cache being turned off.
Configuration needs to retrieve the DDR size to generate the correct
region. Access to the size fails because the value is still in the data
cache. Flushing the size is mandatory.

Change-Id: I3dd1958f37d806f9c15a5d4151968935f6fe642e
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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refactor(plat/st): map DDR secure at boot

In BL2, the DDR can be mapped as secured in MMU, as no other SW
has access to it during its execution.
The TZC400 configuration is also updated to reflect t

refactor(plat/st): map DDR secure at boot

In BL2, the DDR can be mapped as secured in MMU, as no other SW
has access to it during its execution.
The TZC400 configuration is also updated to reflect this. When using
OP-TEE, the TZC400 is reconfigured at the end of BL2, to match OP-TEE
mapping. Else, SP_min will be in charge to reconfigure TZC400 to set
DDR non-secure.

Change-Id: Ic5ec614b218f733796feeab1cdc425d28cc7c103
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(plat/st): rework TZC400 configuration

Add new static functions to factorize code in stm32mp1_security.c.

Change-Id: Ifa5a1aaf7c56c25dba9a0ab8e985496d7cb06990
Signed-off-by: Yann Gautier <y

refactor(plat/st): rework TZC400 configuration

Add new static functions to factorize code in stm32mp1_security.c.

Change-Id: Ifa5a1aaf7c56c25dba9a0ab8e985496d7cb06990
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "refactor(plat/qemu): increase the non-secure DRAM size" into integration

fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive

For UART secure boot it is required also TIMN image, so pack it into
uart-images.tgz.bin archive which is created by mrvl_uart target.

fix(plat/marvell/a3k): Fix building uart-images.tgz.bin archive

For UART secure boot it is required also TIMN image, so pack it into
uart-images.tgz.bin archive which is created by mrvl_uart target.

$(TIMN_IMAGE) and $(TIM_IMAGE) variables are used only for UART images
so their content needs to be initialized from $(TIMN_UART_CFG) and
$(TIM_UART_CFG) config files. And not from $(TIMN_CFG) and $(TIM_CFG) as
it is now because they are not generated during mrvl_uart target. Fix it
to allow building mrvl_uart target before mrvl_flash target.

To match usage of these variables, rename them to $(TIMN_UART_IMAGE) and
$(TIM_UART_IMAGE).

To not complicate rule for building uart-images.tgz.bin archive, set
list of image files into a new $(UART_IMAGES) variable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I83b980abb4047a3afb3ce3026842e1d873c490bf

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refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables

For TIM config file use TIM name instead of DOIMAGE and use underscores
to make variable names more readable.

Signed-off-by: Pali Rohár

refactor(plat/marvell/a3k): Rename *_CFG and *_SIG variables

For TIM config file use TIM name instead of DOIMAGE and use underscores
to make variable names more readable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1282ce11f1431c15458a143ae7bfcee85eed2432

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feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked

In case the RCAR_RPC_HYPERFLASH_LOCKED is 0, emit DT node /soc/rpc@ee200000
with property status = "okay" into the DT fragment passed

feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked

In case the RCAR_RPC_HYPERFLASH_LOCKED is 0, emit DT node /soc/rpc@ee200000
with property status = "okay" into the DT fragment passed to subsequent
software, to indicate the RPC is unlocked.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id93c4573ab1c62cf13fa5a803dc5818584a2c13a

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refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB

Armada 3700 uses external TBB tool for creating images and does not use
internal TF-A doimage tool from tools/marvell/doimage/

Therefore set co

refactor(plat/marvell/a3k): Rename DOIMAGETOOL to TBB

Armada 3700 uses external TBB tool for creating images and does not use
internal TF-A doimage tool from tools/marvell/doimage/

Therefore set correct name of variable.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I38a94dca78d483de4c79da597c032e1e5d06d92d

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refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable

Armada 3700 uses WTP so use WTP variable directly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I216b40ffee1f3f8abba4677f05

refactor(plat/marvell/a3k): Remove useless DOIMAGEPATH variable

Armada 3700 uses WTP so use WTP variable directly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I216b40ffee1f3f8abba4677f050ab376c2224ede

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fix(plat/marvell/a3k): Fix check for external dependences

Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Ext

fix(plat/marvell/a3k): Fix check for external dependences

Old Marvell a3700_utils and mv-ddr tarballs do not have to work with
latest TF-A code base. Marvell do not provide these old tarballs on
Extranet anymore. Public version on github repository contains all
patches and is working fine, so for public TF-A builds use only public
external dependencies from git.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iee5ac6daa9a1826a5b80a8d54968bdbb8fe72f61

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fix(plat/marvell/a8k): Add missing build dependency for BLE target

BLE source files depend on external Marvell mv-ddr-marvell tree
(specified in $(MV_DDR_PATH) variable) and its header files. Add
de

fix(plat/marvell/a8k): Add missing build dependency for BLE target

BLE source files depend on external Marvell mv-ddr-marvell tree
(specified in $(MV_DDR_PATH) variable) and its header files. Add
dependency on $(MV_DDR_LIB) target which checks that variable
$(MV_DDR_PATH) is correctly set and ensures that make completes
compilation of mv-ddr-marvell tree.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I73968b24c45d9af1e3500b8db7a24bb4eb2bfa47

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fix(plat/marvell/a8k): Correctly set include directories for individual targets

Do not set all include directories, including those for external targets
in one PLAT_INCLUDES variable.

Instead split

fix(plat/marvell/a8k): Correctly set include directories for individual targets

Do not set all include directories, including those for external targets
in one PLAT_INCLUDES variable.

Instead split them into variables:
* $(PLAT_INCLUDES) for all TF-A BL images
* BLE target specific $(PLAT_INCLUDES) only for Marvell BLE image
* $(MV_DDR_INCLUDES) for targets in external Marvell mv-ddr-marvell tree

Include directory $(CURDIR)/drivers/marvell is required by TF-A BL
images, so move it from ble.mk to a8k_common.mk.

Include directory $(MV_DDR_PATH) is needed only by Marvell BLE image, so
move it into BLE target specific $(PLAT_INCLUDES) variable.

And remaining include directories specified in ble.mk are needed only
for building external dependences from Marvell mv-ddr tree, so move them
into $(MV_DDR_INCLUDES) variable and correctly use it in $(MV_DDR_LIB)
target.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I331f7de675dca2bc70733d56b768f00d56ae4a67

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fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set

Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded a

fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly set

Target mrvl_flash depends on external mv_ddr source code which is not
part of TF-A project. Do not expect that it is pre-downloaded at some
specific location and require user to specify correct path to mv_ddr
source code via MV_DDR_PATH build option.

TF-A code for Armada 37x0 platform also depends on mv_ddr source code
and already requires passing correct MV_DDR_PATH build option.

So for A8K implement same checks for validity of MV_DDR_PATH option as
are already used by TF-A code for Armada 37x0 platform.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a

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feat(plat/rcar3): add a DRAM size setting for M3N

This commit adds a DRAM size setting when building with
RCAR_DRAM_LPDDR4_MEMCONF=2 for M3N Ver.1.1 4GB DRAM.

Signed-off-by: Toshiyuki Ogasahara <to

feat(plat/rcar3): add a DRAM size setting for M3N

This commit adds a DRAM size setting when building with
RCAR_DRAM_LPDDR4_MEMCONF=2 for M3N Ver.1.1 4GB DRAM.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ib7fea862ab2e0bcafaf39ec030384f0fddda9b96

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feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-

feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0

Update the revision number in the revision management file.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I44b9e5a992e8a44cfeafad6d2c1a97aa59baca4e

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feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB

Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Si

feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB

Add new board revision for 8GB 1rank of Salvator-XS/H3ULCB

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I9e0ef7340d92de9c892fc5bd04abe24ad6ee4286

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fix(drivers/rcar3): fix CPG registers redefinition

This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by

fix(drivers/rcar3): fix CPG registers redefinition

This commit deletes the value of the redefined CPG register.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de

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