Merge "feat(board/rdn2): add tzc master source ids for soc dma" into integration

fix(arm_fpga): reserve BL31 memory

Embarrassingly we never told the non-secure world that secure firmware
lives in the first few hundred KBs of DRAM, so any non-secure payload
could happily overwrit

fix(arm_fpga): reserve BL31 memory

Embarrassingly we never told the non-secure world that secure firmware
lives in the first few hundred KBs of DRAM, so any non-secure payload
could happily overwrite TF-A, and we couldn't even blame it.

Advertise the BL31 region in the reserved-memory DT node, so non-secure
world stays out of it.

This fixes Linux booting on FPGAs with less memory than usual.

Change-Id: I7fbe7d42c0b251c0ccc43d7c50ca902013d152ec
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes I3c20611a,Ib1671011,I5eab3f33,Ib149b3ea into integration

* changes:
refactor(plat/nxp): refine api to read SVR register
refactor(plat/nxp): each errata use a seperate source file

Merge changes I3c20611a,Ib1671011,I5eab3f33,Ib149b3ea into integration

* changes:
refactor(plat/nxp): refine api to read SVR register
refactor(plat/nxp): each errata use a seperate source file
refactor(plat/nxp): use a unified errata api
refactor(plat/soc-lx2160): move errata to common directory

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fix(arm_fpga): limit BL31 memory usage

At the moment we specified the BL31 memory limits to 1MB; since we
typically have gigabytes of DRAM, we can be quite generous.

However the default parameters

fix(arm_fpga): limit BL31 memory usage

At the moment we specified the BL31 memory limits to 1MB; since we
typically have gigabytes of DRAM, we can be quite generous.

However the default parameters expect the devicetree binary at
0x80070000, so we should actually make sure we have no code or data
beyond that point.

Limit the ARM FPGA BL31 memory footprint to this available 7*64K region.
We stay within the limit at the moment, with more than half of it
reserved for stacks, so this could be downsized later should we run
into problems.

The PIE addresses stay as they are, since the default addresses do not
apply there anywhere, and the build is broken anyway.

Change-Id: I7768af1a93ff67096f4359fc5f5feb66464bafaa
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(fvp): enable external SP images in BL2 config

Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Ser

feat(fvp): enable external SP images in BL2 config

Currently the list of SP UUIDs loaded by BL2 is hardcoded in the DT.
This is a problem when building a system with other SPs (e.g. from
Trusted Services). This commit implements a workaround to enable adding
SP UUIDs to the list at build time.

Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Change-Id: Iff85d3778596d23d777dec458f131bd7a8647031

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feat(arm_fpga): support GICv4 images

Up until now we relied on the GICs used in our FPGA images to be GICv3
compliant, without the "direct virtual injection" feature (aka GICv4)
enabled.
To support

feat(arm_fpga): support GICv4 images

Up until now we relied on the GICs used in our FPGA images to be GICv3
compliant, without the "direct virtual injection" feature (aka GICv4)
enabled.
To support newer images which have GICv4 compliant GICs, enable the
newly introduced GICv4 detection code, and use that also when we adjust
the redistributor region size in the devicetree.

This allows the same BL31 image to be used with GICv3 or GICv4 FPGA
images.

Change-Id: I9f6435a6d5150983625efe3650a8b7d1ef11b1d1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec

feat(gicv3): detect GICv4 feature at runtime

At the moment we have a GIC_ENABLE_V4_EXTN build time variable to
determine whether the GIC interrupt controller is compliant to version
4.0 of the spec or not. This just changes the number of 64K MMIO pages
we expect per redistributor.

To support firmware builds which run on variable systems (emulators,
fast model or FPGAs), let's make this decision at runtime.
The GIC specification provides several architected flags to learn the
size of the MMIO frame per redistributor, we use GICR_TYPER[VLPI] here.

Provide a (static inline) function to return the size of each
redistributor.
We keep the GIC_ENABLE_V4_EXTN build time variable around, but change
its meaning to enable this autodetection code. Systems not defining this
rely on a "pure" GICv3 (as before), but platforms setting it to "1" can
now deal with both configurations.

Change-Id: I9ede4acf058846157a0a9e2ef6103bf07c7655d9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(plat/fvp): enable trace extension features by default

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I3e344b0abda7ab4e54ee918ec65ff39d40855fcd

refactor(plat/nxp): refine api to read SVR register

1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster num

refactor(plat/nxp): refine api to read SVR register

1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster numbers and cores per cluster.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4

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feat(plat/marvell): introduce t9130_cex7_eval

This patch adds the necessary files to support
the SolidRun CN913X CEx7 Evaluation Board.

Because the DRAM connectivity and SerDes settings
is shared w

feat(plat/marvell): introduce t9130_cex7_eval

This patch adds the necessary files to support
the SolidRun CN913X CEx7 Evaluation Board.

Because the DRAM connectivity and SerDes settings
is shared with the CN913X DB - reuse relevant
board-specific files.

Change-Id: I75a4554a4373953ca3fdf3b04c4a29c2c4f8ea80
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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feat(plat/marvell/a8k): allow overriding default paths

The common makefile used by every a8k/cn913x platform
(a8k_common.mk) assumed default paths in PLAT_INCLUDES,
BLE/BL31_PORTING_SOURCES. Allow o

feat(plat/marvell/a8k): allow overriding default paths

The common makefile used by every a8k/cn913x platform
(a8k_common.mk) assumed default paths in PLAT_INCLUDES,
BLE/BL31_PORTING_SOURCES. Allow overriding those
variables, in order to avoid code duplication.

It can be helpful in case using multiple board variants
or sharing common settings between different platforms.

Change-Id: Idce603e44ed04d99fb1e3e11a2bb395d552e2bf7
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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Merge changes from topic "allwinner-r329" into integration

* changes:
feat(plat/allwinner): add R329 support
refactor(plat/allwinner): allow custom BL31 offset
refactor(plat/allwinner): allow

Merge changes from topic "allwinner-r329" into integration

* changes:
feat(plat/allwinner): add R329 support
refactor(plat/allwinner): allow custom BL31 offset
refactor(plat/allwinner): allow new AA64nAA32 position
fix(plat/allwinner): delay after enabling CPU power

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Merge "cpu: add support for Demeter CPU" into integration

refactor(plat/nxp): each errata use a seperate source file

Don't mix erratas together in one file.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ib1671011b91a41b0653210e4706d62b7e946c642

refactor(plat/nxp): use a unified errata api

Use a unfied API soc_errata() for each platforms,
add print a INFO message for each enabled errata,
so that it will be easy to check which errata is
enab

refactor(plat/nxp): use a unified errata api

Use a unfied API soc_errata() for each platforms,
add print a INFO message for each enabled errata,
so that it will be easy to check which errata is
enabled on current platform.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5eab3f338db6b46c57cbad475819043fc60ca6d3

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refactor(plat/soc-lx2160): move errata to common directory

Will add more Erratas, some errata can be used for multiple
platforms, so move errata to be common code which can
be share between differen

refactor(plat/soc-lx2160): move errata to common directory

Will add more Erratas, some errata can be used for multiple
platforms, so move errata to be common code which can
be share between different platforms.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ib149b3eac365bdb593331e9f38f0b89d92c9c0d1

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feat(plat/allwinner): add R329 support

Allwinner R329 is a new dual-core Corte-A53 SoC. Add basical TF-A
support for it, to provide a PSCI implementation containing CPU
boot/shutdown and SoC reset.

feat(plat/allwinner): add R329 support

Allwinner R329 is a new dual-core Corte-A53 SoC. Add basical TF-A
support for it, to provide a PSCI implementation containing CPU
boot/shutdown and SoC reset.

Change-Id: I0fa37ee9b4a8e0e1137bf7cf7d614b6ca9624bfe
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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refactor(plat/allwinner): allow custom BL31 offset

Not all Allwinner SoCs have the same arrangement to SRAM A2.

Allow to specify a offset at which BL31 will stay in SRAM A2.

Change-Id: I574140ffd7

refactor(plat/allwinner): allow custom BL31 offset

Not all Allwinner SoCs have the same arrangement to SRAM A2.

Allow to specify a offset at which BL31 will stay in SRAM A2.

Change-Id: I574140ffd704a796fae0a5c2d0976e85c7fcbdf9
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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refactor(plat/allwinner): allow new AA64nAA32 position

In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Clus

refactor(plat/allwinner): allow new AA64nAA32 position

In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.

Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.

Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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fix(plat/allwinner): delay after enabling CPU power

Adds a 1us delay after enabling power to a CPU core, to prevent
inrush-caused CPU crash before it's up.

Change-Id: I8f4c1b0dc0d1d976b31ddc30efe7a

fix(plat/allwinner): delay after enabling CPU power

Adds a 1us delay after enabling power to a CPU core, to prevent
inrush-caused CPU crash before it's up.

Change-Id: I8f4c1b0dc0d1d976b31ddc30efe7a77a1619b1b3
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>

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Merge "fix(rpi4): drop /memreserve/ region" into integration

feat(board/rdn2): add tzc master source ids for soc dma

Add TZC master source id for DMA in the SoC space and for the DMAs
behind the I/O Virtualization block to allow the non-secure transactions
fr

feat(board/rdn2): add tzc master source ids for soc dma

Add TZC master source id for DMA in the SoC space and for the DMAs
behind the I/O Virtualization block to allow the non-secure transactions
from these DMAs targeting DRAM.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I77a2947b01b4b49a7c1940f09cf62b7b5257657c

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fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default

It was enabled in commit 3c7dcdac5c50 ("marvell/a3700: Prevent SError
accessing PCIe link while it is down") with a workaround for a bug

fix(plat/marvell/a3k): disable HANDLE_EA_EL3_FIRST by default

It was enabled in commit 3c7dcdac5c50 ("marvell/a3700: Prevent SError
accessing PCIe link while it is down") with a workaround for a bug found
in U-Boot and Linux kernel driver pci-aardvark.c (PCIe controller driver
for Armada 37xx SoC) which results in SError interrupt caused by AXI
SLVERR on external access (syndrome 0xbf000002) and immediate kernel
panic.

Now when proper patches are in both U-Boot and Linux kernel projects,
this workaround in TF-A should not have to be enabled by default
anymore as it has unwanted side effects like propagating all external
aborts, including non-fatal/correctable into EL3 and making them as
fatal which cause immediate abort.

Add documentation for HANDLE_EA_EL3_FIRST build option into Marvell
Armada build section.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic92b65bf9923505ab682830afb66c2f6cec70491

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fix(plat/marvell/a3k): update information about PCIe abort hack

A3700 plat_ea_handler was introduced into TF-A codebase just because of
bugs in U-Boot and Linux kernel PCIe controller driver pci-aar

fix(plat/marvell/a3k): update information about PCIe abort hack

A3700 plat_ea_handler was introduced into TF-A codebase just because of
bugs in U-Boot and Linux kernel PCIe controller driver pci-aardvark.c.

These bugs were finally fixed in both U-Boot and Linux kernel drivers:
https://source.denx.de/u-boot/u-boot/-/commit/eccbd4ad8e4e182638eafbfb87ac139c04f24a01
https://git.kernel.org/stable/c/f18139966d072dab8e4398c95ce955a9742e04f7

Add all these information into comments, including printing error
message into a3k plat_ea_handler. Also check that abort is really
asynchronous and comes from lower level than EL3.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I46318d221b39773d5e25b3a0221d7738736ffdf1

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Merge changes I976aef15,I11ae679f into integration

* changes:
feat(plat/xilinx/zynqmp): add support for runtime feature config
feat(plat/xilinx/zynqmp): sync IOCTL IDs