1 /* 2 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <drivers/delay_timer.h> 14 #include <lib/mmio.h> 15 #include <lib/utils_def.h> 16 #include <plat/common/platform.h> 17 18 #include <sunxi_cpucfg.h> 19 #include <sunxi_mmap.h> 20 #include <sunxi_private.h> 21 22 static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core) 23 { 24 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff) 25 return; 26 27 VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core); 28 29 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff); 30 } 31 32 static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core) 33 { 34 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0) 35 return; 36 37 VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core); 38 39 /* Power enable sequence from original Allwinner sources */ 40 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe); 41 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8); 42 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0); 43 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80); 44 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00); 45 udelay(1); 46 } 47 48 /* We can't turn ourself off like this, but it works for other cores. */ 49 static void sunxi_cpu_off(u_register_t mpidr) 50 { 51 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); 52 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 53 54 VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core); 55 56 /* Deassert DBGPWRDUP */ 57 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 58 /* Activate the core output clamps, but not for core 0. */ 59 if (core != 0) 60 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); 61 /* Assert CPU power-on reset */ 62 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 63 /* Remove power from the CPU */ 64 sunxi_cpu_disable_power(cluster, core); 65 } 66 67 void sunxi_cpu_on(u_register_t mpidr) 68 { 69 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); 70 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 71 72 VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core); 73 74 /* Assert CPU core reset */ 75 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 76 /* Assert CPU power-on reset */ 77 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 78 /* Set CPU to start in AArch64 mode */ 79 mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core)); 80 /* Apply power to the CPU */ 81 sunxi_cpu_enable_power(cluster, core); 82 /* Release the core output clamps */ 83 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); 84 /* Deassert CPU power-on reset */ 85 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); 86 /* Deassert CPU core reset */ 87 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); 88 /* Assert DBGPWRDUP */ 89 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); 90 } 91 92 void sunxi_cpu_power_off_others(void) 93 { 94 u_register_t self = read_mpidr(); 95 unsigned int cluster; 96 unsigned int core; 97 98 for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; ++cluster) { 99 for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) { 100 u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) | 101 (core << MPIDR_AFF0_SHIFT) | 102 BIT(31); 103 if (mpidr != self) 104 sunxi_cpu_off(mpidr); 105 } 106 } 107 } 108