feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then

feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP

Adds bl2 with FIP to the build required for mbed Linux booting where
we do:

BootROM -> SPL -> BL2 -> OPTEE -> u-boot

If NEED_BL2 is specified then BL2 will be built and BL31 will have its
address range modified upwards to accommodate. BL31 must be loaded from a
FIP in this case.

If NEED_BL2 is not specified then the current BL31 boot flow is unaffected
and u-boot SPL will load and execute BL31 directly.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I78914d6002755f733ea866127cb47982a00f9700

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refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common

This commit makes the image load logic from imx8mm common for all
imx8m platform.

Signed-off-by: Ying-Chun Liu (PaulLiu)

refactor(plat/imx/imx8m): make image load logic for TBBR FIP booting common

This commit makes the image load logic from imx8mm common for all
imx8m platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Ibfe2e9cc09d198cb9e309afaf381a0237a4b82ed

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feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout

Adds a number of definitions consistent with the established RSB3720
equivalents specifying number of io_handles and bloc

feat(plat/imx/imx8m/imx8mp): add initial definition to facilitate FIP layout

Adds a number of definitions consistent with the established RSB3720
equivalents specifying number of io_handles and block devices.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I401e48216d67257137351ee4d0b98904a76fa789

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refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common

This commit makes imx image io-storage logic common for all
imx platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debia

refactor(plat/imx/imx): make imx io-storage logic for TBBR/FIP common

This commit makes imx image io-storage logic common for all
imx platform.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: I15045ac8f9dfa8cb714e32f9e7475d5eae4e86e4

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feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build

Allows for exporting of FIP related methods cleanly in a private header.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
C

feat(plat/imx/imx8m/imx8mp): add imx8mp_private.h to the build

Allows for exporting of FIP related methods cleanly in a private header.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Iaaad4e69ef89c8a8a74648647d7fd09cd0fdd12a

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fix(plat/synquacer): update scmi power domain off handling

In the SCMI power domain off handling, configure GIC
to prevent interrupt toward to the core to be turned off,
and configure CCN to disable

fix(plat/synquacer): update scmi power domain off handling

In the SCMI power domain off handling, configure GIC
to prevent interrupt toward to the core to be turned off,
and configure CCN to disable coherency when the cluster is turned off.
The same operation is done in SCPI power domain off processing.

This commit adds the missing operation in SCMI power domain
off handling.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: Ib3523de488500c2e8bdc74e4cb8772a1442d9781

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feat(plat/mediatek/mt8195): add vcore-dvfs support

Add DVFSRC init flow.

Change-Id: Ic5fc78c91359abc12c0f54b01860a7cbe41f3358
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>

Merge "fix(plat/qti/sc7180): qti smc addition" into integration

feat(plat/rcar3): keep RWDT enabled

In case the WDT is enabled by prior stage, keep it enabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie7c0eaf2f59dd8c30a9ef686a70004

feat(plat/rcar3): keep RWDT enabled

In case the WDT is enabled by prior stage, keep it enabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ie7c0eaf2f59dd8c30a9ef686a7000424f38d6352

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feat(plat/rcar3): modify LifeC register setting for R-Car D3

Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by

feat(plat/rcar3): modify LifeC register setting for R-Car D3

Modified SECGRP0COND6 and SECGRP1COND6 setting for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I3f173ac44c11743965c013ef238748b0dc8cabab

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feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3

Because the Realtime module stop control register n (RMSTPCRn)
are not supported in R-Car D3. Therefore, remove access to these
regi

feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3

Because the Realtime module stop control register n (RMSTPCRn)
are not supported in R-Car D3. Therefore, remove access to these
registers in R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I4647e28d0e176ff97151e9842019ba12cefe5c03

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feat(plat/rcar3): add process of SSCG setting for R-Car D3

- Added the condition where output the SSCG (MD12) setting
to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by

feat(plat/rcar3): add process of SSCG setting for R-Car D3

- Added the condition where output the SSCG (MD12) setting
to log for R-Car D3.
- Added the process to switching the bit rate of SCIF by the
SSCG (MD12) setting value for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Iaf07fa4df12dc233af0b57569ee4fa9329f670a9

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feat(plat/rcar3): add process to back up X6 and X7 register's value

Because the x6 and x7 registers will be overwritten by the callee function,
added the processing the register's value push to/pop

feat(plat/rcar3): add process to back up X6 and X7 register's value

Because the x6 and x7 registers will be overwritten by the callee function,
added the processing the register's value push to/pop from stack memory.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I5351a008d3b208a30a8bc8651b8d9b4d1a02a8e8

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feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up

Added the process of SYSECEXTMASK bit set/clear for following
power Resume/Shutoff flow.

Signed-off-by: Hideyuki Nitta <hideyuki.nitt

feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up

Added the process of SYSECEXTMASK bit set/clear for following
power Resume/Shutoff flow.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I71ed22840a42e7ab7d87bfd4241eec6f5ddb129b

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feat(plat/rcar3): change the memory map for OP-TEE

The memory area size of OP-TEE was changed from 1MB to 2MB
because the size of OP-TEE has increased.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki

feat(plat/rcar3): change the memory map for OP-TEE

The memory area size of OP-TEE was changed from 1MB to 2MB
because the size of OP-TEE has increased.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Ic8a165c83a3a9ef2829f68d5fabeed9ccb6da95e

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feat(plat/rcar3): use PRR cut to determine DRAM size on M3

The new M3 DRAM size can be determined by the PRR cut version.
Read the PRR cut version, and if it is older than cut 30, use
legacy DRAM si

feat(plat/rcar3): use PRR cut to determine DRAM size on M3

The new M3 DRAM size can be determined by the PRR cut version.
Read the PRR cut version, and if it is older than cut 30, use
legacy DRAM size scheme, else report 8GB in 2GBx4 2ch split.

Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # Fix DRAM size judgment by PRR register, reword commit message
Change-Id: Ib83176d0d09cab5cae0119ba462e42c66c642798

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feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537

Apply ERRATA_A53_1530924 and ERRATA_A57_1319537.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: T

feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537

Apply ERRATA_A53_1530924 and ERRATA_A57_1319537.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # Drop Makefile header change, reword commit message
Change-Id: I7d6e7e40bad6545a1d96470ce1a6e2d04e042670

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fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3

Fix disabling MFIS write protection for R-Car D3.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by:

fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3

Fix disabling MFIS write protection for R-Car D3.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I8bb5787c09c53dff55d6de89adfcb71157533976

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fix(plat/rcar3): fix eMMC boot support for R-Car D3

Fix to support of booting from eMMC (50MHz x 8) on
Draak board for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed

fix(plat/rcar3): fix eMMC boot support for R-Car D3

Fix to support of booting from eMMC (50MHz x 8) on
Draak board for R-Car D3.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I0ab2b5c7f8075acbf5f4a69694fb535dddc1a4c8

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fix(plat/rcar3): fix version judgment for R-Car D3

Added the process of judgment and logging for R-Car D3 Ver.1.1 and Ver.1.0.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-o

fix(plat/rcar3): fix version judgment for R-Car D3

Added the process of judgment and logging for R-Car D3 Ver.1.1 and Ver.1.0.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I326aa42374b70b6a4a71893561a7eaa0b6eddef0

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fix(plat/rcar3): fix source file to make about GICv2

Changed the plat/renesas/common/common.mk to change the source files
about GICv2 by include gicv2.mk, because gic_common.c has deprecated.

Signe

fix(plat/rcar3): fix source file to make about GICv2

Changed the plat/renesas/common/common.mk to change the source files
about GICv2 by include gicv2.mk, because gic_common.c has deprecated.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: Iaa7eae6b2c1dd79a05339325e6bc422d87bce49e

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Merge changes from topic "gic-700-auto" into integration

* changes:
feat(arm_fpga): support GICv4 images
feat(gicv3): detect GICv4 feature at runtime
feat(gicv3): multichip: detect GIC-700 at

Merge changes from topic "gic-700-auto" into integration

* changes:
feat(arm_fpga): support GICv4 images
feat(gicv3): detect GICv4 feature at runtime
feat(gicv3): multichip: detect GIC-700 at runtime
refactor(gic): move GIC IIDR numbers
refactor(gicv3): rename GIC Clayton to GIC-700

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Merge "fix(plat/marvell/a3k): enable workaround for erratum 1530924" into integration

Merge "feat(plat/st): add a new DDR firewall management" into integration

Merge changes from topic "st_fip_fconf" into integration

* changes:
refactor(plat/st): use TZC400 bindings
feat(dt-bindings): add STM32MP1 TZC400 bindings