feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53

Add new function so that the value of bit at WUPMSKCA57/53,
which points to CPU other than the BOOT CPU, is 1 at initialization.

feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53

Add new function so that the value of bit at WUPMSKCA57/53,
which points to CPU other than the BOOT CPU, is 1 at initialization.
Modify sequence so that value of each bit for CPU at WUPMSKCA57/53 is
basically 0 and target bit value is changed to 1 only when CPU_OFF.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id5dafc04e1dbaf265c8b67b903c335bb1af49914

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Merge "feat(plat/zynqmp): disable the -mbranch-protection flag" into integration

Merge changes from topic "mb_critical_data" into integration

* changes:
docs(measured-boot): add a platform function for critical data
feat(fvp): measure critical data

feat(plat/zynqmp): disable the -mbranch-protection flag

With new gcc11.2 by default the -mbranch-protection is
set to "standard" which is leading to increase the text
section by 4Kb. As the ZynqMP u

feat(plat/zynqmp): disable the -mbranch-protection flag

With new gcc11.2 by default the -mbranch-protection is
set to "standard" which is leading to increase the text
section by 4Kb. As the ZynqMP uses the ARMv8 architecture,
so there is no impact when we disable the branch protection.
These instructions do not provide the branch protection in
architectures before Armv8.3-A.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I36f7a55abf99f50df2ee265255598d83b1f480c6

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Merge "refactor(measured-boot): add generic macros for using Crypto library" into integration

Merge "fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN" into integration

Merge "refactor(plat/synquacer): update PSCI system_off handling" into integration

feat(fvp): measure critical data

Implemented a platform function 'plat_mboot_measure_critical_data' to
measure critical data and record its measurement using the Event Log
driver.
'bl2_plat_mboot_fi

feat(fvp): measure critical data

Implemented a platform function 'plat_mboot_measure_critical_data' to
measure critical data and record its measurement using the Event Log
driver.
'bl2_plat_mboot_finish' function invokes this platform function
immediately after populating the critical data.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia198295c6e07ab26d436eab1ff90df2cf28303af

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refactor(measured-boot): add generic macros for using Crypto library

It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in

refactor(measured-boot): add generic macros for using Crypto library

It doesn't look correct to use mbed TLS defines directly in the Event
Log driver as this driver may use another Crypto library in future.
Hence mbed TLS Crypto dependency on Event Log driver is removed by
introducing generic Crypto defines and uses those in the Event Log
driver to call Crypto functions.
Also, updated mbed TLS glue layer to map these generic Crypto defines
to mbed TLS library defines.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ibc9c751f60cbce4d3f3cf049b7c53b3d05cc6735

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Merge "refactor(measured boot): rename a macro INVALID_ID to EVLOG_INVALID_ID" into integration

refactor(plat/synquacer): update PSCI system_off handling

SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP)
which manages system power.
This commit modifies the PSCI system_off handli

refactor(plat/synquacer): update PSCI system_off handling

SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP)
which manages system power.
This commit modifies the PSCI system_off handling to call SCMI,
same as other PSCI calls. System power-off is done by turing off
the ATX power supply through GPIO, this operation is transferred
to SCP.

Note that this commit modifies only the SCMI case, obsolete SCPI
implementation is not updated.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I6c1009e67cccd1eb5d14c338c3df9103d63709dd

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fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN

The GTimer implemented on SynQuacer has similar issue found on Juno
wherein CNTBaseN.CNTFRQ can be written but does not reflec

fix(plat/socionext/synquacer): initialise CNTFRQ in Non Secure CNTBaseN

The GTimer implemented on SynQuacer has similar issue found on Juno
wherein CNTBaseN.CNTFRQ can be written but does not reflect the value
of the CNTFRQ register in CNTCTLBase frame. This doesn't follow ARM ARM
in that the value updated in CNTCTLBase.CNTFRQ is not reflected
in CNTBaseN.CNTFRQ.

Hence enable the workaround (applied to Juno) for SynQuacer that updates
the CNTFRQ register in the Non Secure CNTBaseN frame.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I5204fb57f28c0945812814f008c4905ef0882e2b

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Merge changes from topic "st_uart" into integration

* changes:
feat(plat/st): add STM32MP_UART_PROGRAMMER target
feat(plat/st): add STM32CubeProgrammer support on UART
feat(drivers/st/uart): a

Merge changes from topic "st_uart" into integration

* changes:
feat(plat/st): add STM32MP_UART_PROGRAMMER target
feat(plat/st): add STM32CubeProgrammer support on UART
feat(drivers/st/uart): add uart driver for STM32MP1

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feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP

1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:20

feat(plat/mediatek/mt8195): add EMI MPU surppot for SCP and DSP

1. Enable domain D0 and D3 (SCP) access 0x50000000~0x51400000.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:204347737
TEST=build pass

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I7c9f8490b8898008ba6844c34c9e80caa6066cbc

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feat(plat/mediatek/mt8195): dump EMI MPU configurations

Add dump_emi_mpu_regions() to dump EMI MPU configurations.

BUG=b:204347737
TEST=build pass

Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1

feat(plat/mediatek/mt8195): dump EMI MPU configurations

Add dump_emi_mpu_regions() to dump EMI MPU configurations.

BUG=b:204347737
TEST=build pass

Change-Id: Ia92c6d19b96d429682dff1680d5f5b2dc2bc1b8f
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>

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Merge "fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds" into integration

feat(plat/st): add STM32MP_UART_PROGRAMMER target

Handle boot from UART with STM32CubeProgammer based on mmap io
for STM32MP15.

Depends-On: Iba84e8dfd67b9f30416efb0f6778e48ba1f75dad
Signed-off-by:

feat(plat/st): add STM32MP_UART_PROGRAMMER target

Handle boot from UART with STM32CubeProgammer based on mmap io
for STM32MP15.

Depends-On: Iba84e8dfd67b9f30416efb0f6778e48ba1f75dad
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: Ibd719dd46a11da78633728675ef6639635b6cf67

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feat(plat/st): add STM32CubeProgrammer support on UART

Add a file to support the STMicroelectronics tool STM32CubeProgrammer
over UART in BL2 for STM32MP15x platform.

This tools is based on protoco

feat(plat/st): add STM32CubeProgrammer support on UART

Add a file to support the STMicroelectronics tool STM32CubeProgrammer
over UART in BL2 for STM32MP15x platform.

This tools is based on protocol defined in AN5275,
"USB DFU/USART protocols used in STM32MP1 Series bootloaders"
based on STM32 MCU protocols (AN3155, "USART protocol used
in the STM32 bootloader").

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I956c95d8de0a94d1eb8e61f043651dae7b838170

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feat(plat/marvell/a3k): add north and south bridge reset registers

These registers make it is possible to do external resets of A3700
peripherals. Most peripherals are reset by clearing a particular

feat(plat/marvell/a3k): add north and south bridge reset registers

These registers make it is possible to do external resets of A3700
peripherals. Most peripherals are reset by clearing a particular bit,
but some need setting the bit. Reflect this via "_N" suffix in macro
names.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iacef5e671746b831b5beea9e4fdcc59d8de84edc

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fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds

Commit 4333f95 ("fix(spm_mm): do not compile if SVE/SME is enabled")
introduced a comiple time check to verify if ENABLE_SVE_FOR_NS is

fix(plat/arm/sgi): disable SVE for NS to support SPM_MM builds

Commit 4333f95 ("fix(spm_mm): do not compile if SVE/SME is enabled")
introduced a comiple time check to verify if ENABLE_SVE_FOR_NS is set to
0 when SPM_MM build is enabled. To support SPM_MM builds on SGI/RD
platforms set ENABLE_SVE_FOR_NS to 0.

Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: If78ed7567f6d988795b2bc7f772a883783246964

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Merge changes Ia0d13c3c,I8cf821a4,I1e6a598b,I9c6dd8db,Iaf6db75e, ... into integration

* changes:
fix(plat/xilinx/versal): resolve misra R10.6
fix(plat/xilinx/versal): resolve misra R14.4
fix(p

Merge changes Ia0d13c3c,I8cf821a4,I1e6a598b,I9c6dd8db,Iaf6db75e, ... into integration

* changes:
fix(plat/xilinx/versal): resolve misra R10.6
fix(plat/xilinx/versal): resolve misra R14.4
fix(plat/xilinx/versal): resolve misra R17.7
fix(plat/xilinx/versal): resolve misra R10.3
fix(plat/xilinx/versal): resolve misra R7.2
fix(plat/xilinx/versal): resolve misra R15.7
fix(plat/xilinx/versal): resolve misra R15.6
fix(plat/xilinx/versal): resolve misra R10.1 in pm services
fix(plat/xilinx/versal): resolve misra R20.7 in pm services
fix(plat/xilinx/versal): resolve misra R10.3 in pm services
fix(plat/xilinx/versal): resolve misra R10.6 in pm services
fix(plat/xilinx/versal): resolve misra R16.3 in pm services
fix(plat/xilinx/versal): resolve misra R15.6 in pm services

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feat(mt8186): initialize platform for MediaTek MT8186

- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.

TEST=bu

feat(mt8186): initialize platform for MediaTek MT8186

- Add basic platform setup.
- Add MT8186 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Id3e2f46a8c3ab2f3e29137e508d4c671e8f4aad5

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Merge changes I0c1f7d6c,I3bec0b58,If24cf213 into integration

* changes:
feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop S

Merge changes I0c1f7d6c,I3bec0b58,If24cf213 into integration

* changes:
feat(plat/mediatek/apu): add mt8195 APU clock and pll SiP call
feat(plat/mediatek/apu): add mt8195 APU mcu boot and stop SiP call
feat(plat/mediatek/apu): add mt8195 APU iommap regions

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fix(plat/xilinx/versal): resolve misra R10.6

MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
with wider essential type

Signed-off-by:

fix(plat/xilinx/versal): resolve misra R10.6

MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
with wider essential type

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: Ia0d13c3cfeb13d22b6fc7e8869cc713218302973

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fix(plat/xilinx/versal): resolve misra R14.4

MISRA Violation: MISRA-C:2012 R.14.4
- The controlling expression of an if statement and the controlling
expression of an iteration-statement shall hav

fix(plat/xilinx/versal): resolve misra R14.4

MISRA Violation: MISRA-C:2012 R.14.4
- The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean type.

Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I8cf821a42015858200cc0c514600012c8f61061f

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