| 3ccd7e45 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
fix(nxp/common/setup): increase soc name maximum length
Increate SoC name length as it is not enough for some
SoC personalities.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan
fix(nxp/common/setup): increase soc name maximum length
Increate SoC name length as it is not enough for some
SoC personalities.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2142b4b5162dd3c9ab3afefcdc859063836d8bcc
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|
| 3d14a30b | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/common/errata): add SoC erratum a008850
Add SoC erratum a008850 support.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I1ef41c67737b7b5fdf1d892929a2d8040effc282 |
| b759727f | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/common/io): add ifc nor and nand as io devices
Added IFC Nor and NAN flash as boot IO devices.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ie1b87174d9c08d4e32138066b007fef6f8
feat(nxp/common/io): add ifc nor and nand as io devices
Added IFC Nor and NAN flash as boot IO devices.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ie1b87174d9c08d4e32138066b007fef6f8e3c5dd
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|
| bc378a0d | 20-Jan-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(tc): enable tracing" into integration |
| 8be574bf | 17-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp1): use a macro for header size
Use STM32MP_HEADER_RESERVED_SIZE macro instead of a fixed value 0x3000
in linker script.
Change-Id: I2702285c15aebaa1304a891c8aaabc949a912ba6
Signed-
refactor(stm32mp1): use a macro for header size
Use STM32MP_HEADER_RESERVED_SIZE macro instead of a fixed value 0x3000
in linker script.
Change-Id: I2702285c15aebaa1304a891c8aaabc949a912ba6
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| dea02f4e | 12-Jan-2021 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp1): add helper to enable high speed mode in low voltage
This new function is used to fill the register(s) responsible to enable
high speed mode for pad in low voltage (<2.7V).
Change-Id
feat(stm32mp1): add helper to enable high speed mode in low voltage
This new function is used to fill the register(s) responsible to enable
high speed mode for pad in low voltage (<2.7V).
Change-Id: Ib8abc6628bdf51bbe6a866bc6a9bcdeb4a84a8f4
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 1f4513cb | 16-Dec-2020 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp1): add helpers for IO compensation cells
Add enable_io_comp_cell and disable_io_comp_cell local helpers
to enable or disable an IO compensation cell.
Change-Id: I65295298a7ece572ae
refactor(stm32mp1): add helpers for IO compensation cells
Add enable_io_comp_cell and disable_io_comp_cell local helpers
to enable or disable an IO compensation cell.
Change-Id: I65295298a7ece572ae939e2db93d10b188de0f9e
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| c7a66e72 | 07-Feb-2020 |
Etienne Carriere <etienne.carriere@st.com> |
feat(stm32mp1): use clk_enable/disable functions
Use the clock framework functions in SYSCFG driver instead of dedicated
functions.
Change-Id: Ifb50a5207e8cecef1c80d86e2de4d70ab6bf8b8b
Signed-off-b
feat(stm32mp1): use clk_enable/disable functions
Use the clock framework functions in SYSCFG driver instead of dedicated
functions.
Change-Id: Ifb50a5207e8cecef1c80d86e2de4d70ab6bf8b8b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| de02e9b0 | 18-Nov-2019 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(stm32mp1): add timeout in IO compensation
Use a timeout during IO compensation enable function, when
waiting for ready status. If timeout expires, print a warning
message, to indicate that the
feat(stm32mp1): add timeout in IO compensation
Use a timeout during IO compensation enable function, when
waiting for ready status. If timeout expires, print a warning
message, to indicate that the SoC recommendation is not followed.
Change-Id: I98c7dcb1364b832f4f4b5fc9a0b85a3741a8af4b
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| e1c018e8 | 19-Jan-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(imx8mp): change the BL31 physical load address" into integration |
| d374060a | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/common/rcpm): add RCPM2 registers definition
Added some RCPM2 register offset definiton for register: IPSTPCR,
IPSTPACKR and POWMGTDCR, also added OVRD bit definiton of register
POWMGTDCR.
feat(nxp/common/rcpm): add RCPM2 registers definition
Added some RCPM2 register offset definiton for register: IPSTPCR,
IPSTPACKR and POWMGTDCR, also added OVRD bit definiton of register
POWMGTDCR.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I301bc1401e053c2089b5eb3672c6e649c805a2ab
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| 0259a3e8 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
fix(nxp/common/setup): fix total dram size checking
total_dram_size should be signed value because it is equal to return
value of init_ddr(), so if it is lower or equal zero, report
error as DDR is
fix(nxp/common/setup): fix total dram size checking
total_dram_size should be signed value because it is equal to return
value of init_ddr(), so if it is lower or equal zero, report
error as DDR is not initialized correctly.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Idbc40da103f60f10cb18c5306e97b764c1a9d372
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| 3ccc8ac3 | 21-Oct-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(nxp/common): add CORTEX A53 helper functions
Add helper function to disable the load-store prefetch.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I36d7be37e0b800ab1e5842a56cfd04d7
feat(nxp/common): add CORTEX A53 helper functions
Add helper function to disable the load-store prefetch.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I36d7be37e0b800ab1e5842a56cfd04d779338868
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|
| 97c91147 | 13-Jan-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st_mapping_update" into integration
* changes:
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
refactor(stm32mp1): reduce MMU memory regions and spl
Merge changes from topic "st_mapping_update" into integration
* changes:
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
refactor(stm32mp1): reduce MMU memory regions and split XLAT by context
feat(st): map 2MB for ROM code
fix(stm32mp1): restrict DEVICE2 mapping in BL2
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| 635e6b10 | 16-Nov-2021 |
jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> |
feat(mt8186): add Vcore DVFS driver
Add Vcore DVFS to SPM driver.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I52b241b2cdb792be74390cbaa09a
feat(mt8186): add Vcore DVFS driver
Add Vcore DVFS to SPM driver.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I52b241b2cdb792be74390cbaa09a728ddbe6593a
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|
| 7ac6a76c | 16-Nov-2021 |
jason-ch chen <jason-ch.chen@mediatek.corp-partner.google.com> |
feat(mt8186): add SPM suspend driver
Add SPM suspend driver for suspend/resume features.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I25b4b
feat(mt8186): add SPM suspend driver
Add SPM suspend driver for suspend/resume features.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jason-ch Chen <jason-ch.chen@mediatek.com>
Change-Id: I25b4b97cd3138a7b347385539e47ccfa884d64fc
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|
| 59da207e | 13-Oct-2021 |
Davidson K <davidson.kumaresan@arm.com> |
feat(tc): enable tracing
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan
feat(tc): enable tracing
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I3c86c11be2c655a61ecefa3eb2e4e3951577a113
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| d958d10e | 15-Sep-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
Because the BL2 is not relocated, the usage of BL2_IN_XIP_MEM
can be used. It reduces the binary size by removing all relocation
s
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
Because the BL2 is not relocated, the usage of BL2_IN_XIP_MEM
can be used. It reduces the binary size by removing all relocation
sections. XIP will not be used when STM32MP_USE_STM32IMAGE is
defined. Introduce new definitions for SEPARATE_CODE_AND_RODATA.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Ifd76f14e5bc98990bf84e0bfd4ee0b4e49a9a293
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|
| ac1b24d5 | 16-Jan-2020 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp1): reduce MMU memory regions and split XLAT by context
Simplify the BL2 MMU mapping and reduce the memory regions
number. Split the XLAT define between BL2 and BL32 as binaries
do n
refactor(stm32mp1): reduce MMU memory regions and split XLAT by context
Simplify the BL2 MMU mapping and reduce the memory regions
number. Split the XLAT define between BL2 and BL32 as binaries
do not share the same tables anymore.
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iaf09e72b4cc29acbe376f6f1cd2a8116c793ba26
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|
| 1697ad8c | 15-Sep-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(st): map 2MB for ROM code
This allows reducing MMU tables, and as there is nothing after ROM code
in memory mapping, this has no impact.
Change-Id: If51facb96a523770465cb06eb1ab400f75d26db3
Si
feat(st): map 2MB for ROM code
This allows reducing MMU tables, and as there is nothing after ROM code
in memory mapping, this has no impact.
Change-Id: If51facb96a523770465cb06eb1ab400f75d26db3
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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|
| db3e0ece | 17-Sep-2020 |
Yann Gautier <yann.gautier@st.com> |
fix(stm32mp1): restrict DEVICE2 mapping in BL2
Only NAND memory map area can be of interest for BL2 in the
DEVICE2 area. Map DEVICE2 under STM32MP_RAW_NAND flag.
Change-Id: I7e3b39579e4a2525b25cb19
fix(stm32mp1): restrict DEVICE2 mapping in BL2
Only NAND memory map area can be of interest for BL2 in the
DEVICE2 area. Map DEVICE2 under STM32MP_RAW_NAND flag.
Change-Id: I7e3b39579e4a2525b25cb1987d6ec38038d0de2b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| 32d50422 | 15-Dec-2021 |
Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> |
fix(imx8mp): change the BL31 physical load address
Change BL31 load address to 0x970000. This was done by Change-Id
I96d572fc. But then changed back to 0x960000 by Change-Id I8308c629.
However, 0x97
fix(imx8mp): change the BL31 physical load address
Change BL31 load address to 0x970000. This was done by Change-Id
I96d572fc. But then changed back to 0x960000 by Change-Id I8308c629.
However, 0x970000 is the correct value thus we change it back again.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Change-Id: Ia0db4877123b89072f723d18e2bcce25ef38f47d
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| d52ed024 | 08-Jan-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(renesas): disable CRYPTO_SUPPORT option
Disabled CRYPTO_SUPPORT option for Renesas platform as it does not
follow the TF-A authentication mechanism where Trusted-Boot mandates
Crypto module
refactor(renesas): disable CRYPTO_SUPPORT option
Disabled CRYPTO_SUPPORT option for Renesas platform as it does not
follow the TF-A authentication mechanism where Trusted-Boot mandates
Crypto module support.
Change-Id: I3aa771e983e3dde083dd8a861f25c0714ffd707f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 88c51c3f | 08-Jan-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot
As Measured-Boot and Trusted-Boot are orthogonal, removed
Trusted-Boot's dependency on Measured-Boot by allowing them
to apply the Crypt
refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot
As Measured-Boot and Trusted-Boot are orthogonal, removed
Trusted-Boot's dependency on Measured-Boot by allowing them
to apply the Crypto module changes independently using the
CRYPTO_SUPPORT build flag.
Change-Id: I5a420e5d84f3fefe0c0092d822dab981e6390bbf
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| e537bcde | 10-Jan-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(mt8195): apply erratas of CA78 for MT8195" into integration |