1 /* 2 * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <common/debug.h> 8 #include <drivers/clk.h> 9 #include <drivers/delay_timer.h> 10 #include <drivers/st/bsec.h> 11 #include <drivers/st/stpmic1.h> 12 #include <lib/mmio.h> 13 14 #include <platform_def.h> 15 #include <stm32mp_dt.h> 16 #include <stm32mp1_private.h> 17 18 /* 19 * SYSCFG REGISTER OFFSET (base relative) 20 */ 21 #define SYSCFG_BOOTR 0x00U 22 #define SYSCFG_IOCTRLSETR 0x18U 23 #define SYSCFG_ICNR 0x1CU 24 #define SYSCFG_CMPCR 0x20U 25 #define SYSCFG_CMPENSETR 0x24U 26 #define SYSCFG_CMPENCLRR 0x28U 27 28 #define CMPCR_CMPENSETR_OFFSET 0x4U 29 #define CMPCR_CMPENCLRR_OFFSET 0x8U 30 31 /* 32 * SYSCFG_BOOTR Register 33 */ 34 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0) 35 #define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4) 36 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4 37 /* 38 * SYSCFG_IOCTRLSETR Register 39 */ 40 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0) 41 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1) 42 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2) 43 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3) 44 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4) 45 46 /* 47 * SYSCFG_ICNR Register 48 */ 49 #define SYSCFG_ICNR_AXI_M9 BIT(9) 50 51 /* 52 * SYSCFG_CMPCR Register 53 */ 54 #define SYSCFG_CMPCR_SW_CTRL BIT(1) 55 #define SYSCFG_CMPCR_READY BIT(8) 56 #define SYSCFG_CMPCR_RANSRC GENMASK(19, 16) 57 #define SYSCFG_CMPCR_RANSRC_SHIFT 16 58 #define SYSCFG_CMPCR_RAPSRC GENMASK(23, 20) 59 #define SYSCFG_CMPCR_ANSRC_SHIFT 24 60 61 #define SYSCFG_CMPCR_READY_TIMEOUT_US 10000U 62 63 /* 64 * SYSCFG_CMPENSETR Register 65 */ 66 #define SYSCFG_CMPENSETR_MPU_EN BIT(0) 67 68 static void enable_io_comp_cell_finish(uintptr_t cmpcr_off) 69 { 70 uint64_t start; 71 72 start = timeout_init_us(SYSCFG_CMPCR_READY_TIMEOUT_US); 73 74 while ((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) { 75 if (timeout_elapsed(start)) { 76 /* Failure on IO compensation enable is not a issue: warn only. */ 77 WARN("IO compensation cell not ready\n"); 78 break; 79 } 80 } 81 82 mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_SW_CTRL); 83 } 84 85 static void disable_io_comp_cell(uintptr_t cmpcr_off) 86 { 87 uint32_t value; 88 89 if (((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) || 90 ((mmio_read_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENSETR_OFFSET) & 91 SYSCFG_CMPENSETR_MPU_EN) == 0U)) { 92 return; 93 } 94 95 value = mmio_read_32(SYSCFG_BASE + cmpcr_off) >> SYSCFG_CMPCR_ANSRC_SHIFT; 96 97 mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC); 98 99 value <<= SYSCFG_CMPCR_RANSRC_SHIFT; 100 value |= mmio_read_32(SYSCFG_BASE + cmpcr_off); 101 102 mmio_write_32(SYSCFG_BASE + cmpcr_off, value | SYSCFG_CMPCR_SW_CTRL); 103 104 mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN); 105 } 106 107 void stm32mp1_syscfg_init(void) 108 { 109 uint32_t bootr; 110 uint32_t otp = 0; 111 uint32_t vdd_voltage; 112 113 /* 114 * Interconnect update : select master using the port 1. 115 * LTDC = AXI_M9. 116 */ 117 mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9); 118 119 /* Disable Pull-Down for boot pin connected to VDD */ 120 bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) & 121 SYSCFG_BOOTR_BOOT_MASK; 122 mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK, 123 bootr << SYSCFG_BOOTR_BOOTPD_SHIFT); 124 125 /* 126 * High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI 127 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection. 128 * It could be disabled for low frequencies or if AFMUX is selected 129 * but the function is not used, typically for TRACE. 130 * If high speed low voltage pad mode is node enable, platform will 131 * over consume. 132 * 133 * WARNING: 134 * Enabling High Speed mode while VDD > 2.7V 135 * with the OTP product_below_2v5 (OTP 18, BIT 13) 136 * erroneously set to 1 can damage the SoC! 137 * => TF-A enables the low power mode only if VDD < 2.7V (in DT) 138 * but this value needs to be consistent with board design. 139 */ 140 if (bsec_read_otp(&otp, HW2_OTP) != BSEC_OK) { 141 panic(); 142 } 143 144 otp = otp & HW2_OTP_PRODUCT_BELOW_2V5; 145 146 /* Get VDD supply */ 147 vdd_voltage = dt_get_pwr_vdd_voltage(); 148 149 /* Check if VDD is Low Voltage */ 150 if (vdd_voltage == 0U) { 151 WARN("VDD unknown"); 152 } else if (vdd_voltage < 2700000U) { 153 mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR, 154 SYSCFG_IOCTRLSETR_HSLVEN_TRACE | 155 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | 156 SYSCFG_IOCTRLSETR_HSLVEN_ETH | 157 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC | 158 SYSCFG_IOCTRLSETR_HSLVEN_SPI); 159 160 if (otp == 0U) { 161 INFO("Product_below_2v5=0: HSLVEN protected by HW\n"); 162 } 163 } else { 164 if (otp != 0U) { 165 ERROR("Product_below_2v5=1:\n"); 166 ERROR("\tHSLVEN update is destructive,\n"); 167 ERROR("\tno update as VDD > 2.7V\n"); 168 panic(); 169 } 170 } 171 172 stm32mp1_syscfg_enable_io_compensation_start(); 173 } 174 175 void stm32mp1_syscfg_enable_io_compensation_start(void) 176 { 177 /* 178 * Activate automatic I/O compensation. 179 * Warning: need to ensure CSI enabled and ready in clock driver. 180 * Enable non-secure clock, we assume non-secure is suspended. 181 */ 182 clk_enable(SYSCFG); 183 184 mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPCR, 185 SYSCFG_CMPENSETR_MPU_EN); 186 } 187 188 void stm32mp1_syscfg_enable_io_compensation_finish(void) 189 { 190 enable_io_comp_cell_finish(SYSCFG_CMPCR); 191 } 192 193 void stm32mp1_syscfg_disable_io_compensation(void) 194 { 195 clk_enable(SYSCFG); 196 197 /* 198 * Deactivate automatic I/O compensation. 199 * Warning: CSI is disabled automatically in STOP if not 200 * requested for other usages and always OFF in STANDBY. 201 * Disable non-secure SYSCFG clock, we assume non-secure is suspended. 202 */ 203 disable_io_comp_cell(SYSCFG_CMPCR); 204 205 clk_disable(SYSCFG); 206 } 207