| 23ac80cc | 17-Feb-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(fvp): extend memory map to include all DRAM memory regions" into integration |
| 8d9c1b3c | 16-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st-format-signedness" into integration
* changes:
feat(stm32mp1): enable format-signedness warning
fix(stm32mp1): correct types in messages
fix(st-pmic): correct verb
Merge changes from topic "st-format-signedness" into integration
* changes:
feat(stm32mp1): enable format-signedness warning
fix(stm32mp1): correct types in messages
fix(st-pmic): correct verbose message
fix(st-sdmmc2): correct cmd_idx type in messages
fix(st-fmc): fix type in message
fix(mtd): correct types in messages
fix(usb): correct type in message
fix(tzc400): correct message with filter
fix(psci): correct parent_node type in messages
fix(libc): correct some messages
fix(fconf): correct image_id type in messages
fix(bl2): correct messages with image_id
show more ...
|
| e8035421 | 23-Dec-2021 |
Federico Recanati <federico.recanati@arm.com> |
fix(fvp): extend memory map to include all DRAM memory regions
Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
w
fix(fvp): extend memory map to include all DRAM memory regions
Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
whole address space.
Configuring all of them to allow tests to access memory also in those
higher memory regions.
FVP memory map:
https://developer.arm.com/documentation/100964/1116/Base-Platform/Base---memory/Base-Platform-memory-map
Note that last row is wrong, describing a non-existing 56bit address,
all region labels should be shifted upward.
Issue has been reported and next release will be correct.
Change-Id: I695fe8e24aff67d75e74635ba32a133342289eb4
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
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|
| ef515f0d | 19-Aug-2021 |
Tony K Nadackal <tony.nadackal@arm.com> |
feat(board/rdedmunds): add support for rdedmunds variant
Add initial support for RD-Edmunds platform. This platform is considered
as a variant of RD-N2 platform with only major change being the CPU
feat(board/rdedmunds): add support for rdedmunds variant
Add initial support for RD-Edmunds platform. This platform is considered
as a variant of RD-N2 platform with only major change being the CPU
which is Demeter instead of Neoverse-N2.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I939d9eac652fa9e76ad002ee5e6107aa79baa013
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|
| 22bbb34a | 15-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "refactor(stm32mp1): move PIE flag to SP_min" into integration |
| cff26c19 | 14-Feb-2022 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp1): enable format-signedness warning
Add the flag -Wformat-signedness to TF_CFLAGS for STM32MP1.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6af18778902b0a4dae1c08735d
feat(stm32mp1): enable format-signedness warning
Add the flag -Wformat-signedness to TF_CFLAGS for STM32MP1.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I6af18778902b0a4dae1c08735d2d070ef3d137ce
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|
| 43bbdca0 | 14-Feb-2022 |
Yann Gautier <yann.gautier@st.com> |
fix(stm32mp1): correct types in messages
Avoid warnings when -Wformat-signedness is enabled.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I0ca41cb96826b4f7f9bcf77909fad110325c1e91 |
| cf89fd57 | 27-Oct-2021 |
Satish Kumar <satish.kumar01@arm.com> |
feat(corstone1000): identify bank to load fip
Secure enclave decides the boot bank based on the firmware update
state of the system and updates the boot bank information at a given
location in the f
feat(corstone1000): identify bank to load fip
Secure enclave decides the boot bank based on the firmware update
state of the system and updates the boot bank information at a given
location in the flash. In this commit, bl2 reads the given flash
location to indentify the bank from which it should load fip from.
Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I7f0f4ffc97189c9deb99db44afcd966082ffbf21
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|
| 5a60efa1 | 14-Feb-2022 |
Pali Rohár <pali@kernel.org> |
fix(a3k): fix comment about BootROM address range
A53 AP BootROM is just 16 kB long and is mapped to address range
0xFFFF0000-0xFFFF4000. RVBAR_EL3 register has value 0xFFFF0000.
A53 AP BootROM itse
fix(a3k): fix comment about BootROM address range
A53 AP BootROM is just 16 kB long and is mapped to address range
0xFFFF0000-0xFFFF4000. RVBAR_EL3 register has value 0xFFFF0000.
A53 AP BootROM itself is in the BootROM window which is 1 MB long and
mapped to address range 0xFFF00000-0xFFFFFFFF.
CM3 BootROM is not accessible from A53 core.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5d4a4c7b1e7550c4738c67a872d341f945d48bbc
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|
| 15594501 | 20-Sep-2021 |
Satish Kumar <satish.kumar01@arm.com> |
fix(corstone1000): change base address of FIP in the flash
More space in the flash is reserved up front for metadata
parser and UEFI variables. That requires change in the flash
base address of wher
fix(corstone1000): change base address of FIP in the flash
More space in the flash is reserved up front for metadata
parser and UEFI variables. That requires change in the flash
base address of where images are present.
Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: Ieaabe09374d707de18d36505c69b6c9a8c2ec2e9
show more ...
|
| a599c80d | 17-Nov-2021 |
Emekcan Aras <Emekcan.Aras@arm.com> |
feat(corstone1000): implement platform specific psci reset
This change implements platform specific psci reset
for the corstone1000.
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Signed-off-by
feat(corstone1000): implement platform specific psci reset
This change implements platform specific psci reset
for the corstone1000.
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I25f77234506416c3376ff4a028f6ea40ebe68437
show more ...
|
| 16662dc4 | 20-Jan-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(ls1046aqds): add board ls1046aqds support
ls1046aqds board is full function board to evaluate ls1046a platform.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: York Sun <york.sun
feat(ls1046aqds): add board ls1046aqds support
ls1046aqds board is full function board to evaluate ls1046a platform.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Id1befe37a25f7c379e76791538348fd03bba78f7
show more ...
|
| b51dc56a | 20-Jan-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(ls1046afrwy): add ls1046afrwy board support
The LS1046A Freeway board (FRWY) is a high-performance computing,
evaluation, and development platform that supports the LS1046A
architecture process
feat(ls1046afrwy): add ls1046afrwy board support
The LS1046A Freeway board (FRWY) is a high-performance computing,
evaluation, and development platform that supports the LS1046A
architecture processor capable of support more than 32,000 CoreMark
performance. The FRWY-LS1046A board supports the LS1046A processor,
onboard DDR4 memory, multiple Gigabit Ethernet, USB3.0 and M2_Type_E
interfaces for Wi-Fi, FRWY-LS1046A-AC includes the Wi-Fi card.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9a9680689e6f17bf4cc76fd5d1883eed6ace5149
show more ...
|
| bb52f756 | 20-Jan-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(ls1046ardb): add ls1046ardb board support
The LS1046A reference design board (RDB) is a high-performance
computing, evaluation, and development platform that supports
the Layerscape LS1046A arc
feat(ls1046ardb): add ls1046ardb board support
The LS1046A reference design board (RDB) is a high-performance
computing, evaluation, and development platform that supports
the Layerscape LS1046A architecture processor.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ib7a01b309e0b0acc7f38e22b138e9e181dff244a
show more ...
|
| cc708597 | 20-Jan-2022 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(ls1046a): add new SoC platform ls1046a
The LS1046A is a cost-effective, power-efficient, and highly
integrated system-on-chip (SoC) design that extends the reach
of the NXP value-performance li
feat(ls1046a): add new SoC platform ls1046a
The LS1046A is a cost-effective, power-efficient, and highly
integrated system-on-chip (SoC) design that extends the reach
of the NXP value-performance line of QorIQ communications
processors. Featuring power-efficient 64-bit Arm Cortex A72
cores with ECC-protected L1 and L2 cache memories for high
reliability, running up to 1.8 GHz.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: rocket <rod.dorris@nxp.com>
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Change-Id: I208d9bf1702410463c2b2630d31d0cd4eb7e8837
show more ...
|
| 854d1c10 | 13-Oct-2021 |
Arpita S.K <Arpita.S.K@arm.com> |
feat(corstone1000): made changes to accommodate 3MB for optee
These changes are required to accommodate 3MB for OP-TEE and this
is required for SP's part of optee
Added size macro's for better reada
feat(corstone1000): made changes to accommodate 3MB for optee
These changes are required to accommodate 3MB for OP-TEE and this
is required for SP's part of optee
Added size macro's for better readability of the code
Moved uboot execution memory from CVM to DDR
Change-Id: I16657c6e336fe7c0fffdee1617d10af8a2c76732
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
show more ...
|
| 0260eb0d | 19-Jan-2022 |
Vishnu Banavath <vishnu.banavath@arm.com> |
build(corstone1000): rename diphda to corstone1000
diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda corstone1000.
Change-Id
build(corstone1000): rename diphda to corstone1000
diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda corstone1000.
Change-Id: I330f3a112d232b99b4721b6bf0236253b068dbba
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
show more ...
|
| cb2c4f93 | 06-Oct-2021 |
Ying-Chun Liu (PaulLiu) <paulliu@debian.org> |
feat(plat/imx/imx8m/imx8mm): add support for measured boot
Add helper functions to generate event log for imx8mm
when MEASURED_BOOT=1.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Ch
feat(plat/imx/imx8m/imx8mm): add support for measured boot
Add helper functions to generate event log for imx8mm
when MEASURED_BOOT=1.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Change-Id: Ifc947d749055787fbda0b39170aa2eb8865b7802
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|
| 2ba3085b | 11-Feb-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(measured-boot): cleanup Event Log makefile" into integration |
| 56e8952f | 09-Feb-2022 |
Yann Gautier <yann.gautier@st.com> |
refactor(stm32mp1): move PIE flag to SP_min
The PIE compilation is used only for BL32, move the ENABLE_PIE to
sp_min-stm32mp1.mk file. Override PIE flags, as sp_min.mk file is
included after the fla
refactor(stm32mp1): move PIE flag to SP_min
The PIE compilation is used only for BL32, move the ENABLE_PIE to
sp_min-stm32mp1.mk file. Override PIE flags, as sp_min.mk file is
included after the flags are set in Makefile.
The BL2_IN_XIP_MEM was added for a feature not yet upstreamed.
It is then removed from platform.mk file.
Change-Id: If055e51e0f160f99cd4e4cf68ca718d4d693119c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
show more ...
|
| 2165f97e | 11-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(common): add SZ_* macros" into integration |
| c870188d | 09-Feb-2022 |
Nicolas Toromanoff <nicolas.toromanoff@foss.st.com> |
refactor(stm32mp1): update tamp_bkpr return type
tamp_bkpr() returns a register address. So use uintptr_t instead of
uin32_t.
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Chan
refactor(stm32mp1): update tamp_bkpr return type
tamp_bkpr() returns a register address. So use uintptr_t instead of
uin32_t.
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Change-Id: I5eddfa525465313dadfec18d128248a968ba74e2
show more ...
|
| 1af59c45 | 08-Feb-2022 |
Yann Gautier <yann.gautier@st.com> |
feat(common): add SZ_* macros
Add the SZ_* macros from 32 to 2G.
This allows removing some defines in raw NAND driver
and STM32MP1 boot device selection code.
Change-Id: I3c4d4959b0f43e785eeb37a43d
feat(common): add SZ_* macros
Add the SZ_* macros from 32 to 2G.
This allows removing some defines in raw NAND driver
and STM32MP1 boot device selection code.
Change-Id: I3c4d4959b0f43e785eeb37a43d03b2906b7fcfbc
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
show more ...
|
| 0e1c3f8c | 07-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(rdn2): add board support for rdn2cfg2 variant" into integration |
| 9b4ed0af | 05-Feb-2022 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
feat(plat/zynqmp): fix section `coherent_ram' will not fit in region `RAM'
Actually BL31_LIMIT is set to 0xffffffff but that doesn't work correctly
with bl31.ld since ". = ALIGN(((1) << (12)));" wil
feat(plat/zynqmp): fix section `coherent_ram' will not fit in region `RAM'
Actually BL31_LIMIT is set to 0xffffffff but that doesn't work correctly
with bl31.ld since ". = ALIGN(((1) << (12)));" will try to fill aligned up
to 0x100000000 included, but the RAM size is 0xffffffff, so this leads to
this build error:
```
bl31.elf section `coherent_ram' will not fit in region `RAM'
/home/br-user/git/upstream/ci-tests/zynqmp_zcu102/host/bin/aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte
```
So let's move BR31_LIMIT to 0x100000000 giving 1 byte more room to fill RAM
up to the end.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Change-Id: Ic0edb8ed159e013f60598a9dd4f50adbf656b38d
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|