1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <drivers/clk.h> 10 #include <drivers/st/stm32_gpio.h> 11 #include <drivers/st/stm32_iwdg.h> 12 #include <lib/mmio.h> 13 #include <lib/xlat_tables/xlat_tables_v2.h> 14 #include <libfdt.h> 15 16 #include <plat/common/platform.h> 17 #include <platform_def.h> 18 19 /* Internal layout of the 32bit OTP word board_id */ 20 #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) 21 #define BOARD_ID_BOARD_NB_SHIFT 16 22 #define BOARD_ID_VARCPN_MASK GENMASK(15, 12) 23 #define BOARD_ID_VARCPN_SHIFT 12 24 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) 25 #define BOARD_ID_REVISION_SHIFT 8 26 #define BOARD_ID_VARFG_MASK GENMASK(7, 4) 27 #define BOARD_ID_VARFG_SHIFT 4 28 #define BOARD_ID_BOM_MASK GENMASK(3, 0) 29 30 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ 31 BOARD_ID_BOARD_NB_SHIFT) 32 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ 33 BOARD_ID_VARCPN_SHIFT) 34 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ 35 BOARD_ID_REVISION_SHIFT) 36 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ 37 BOARD_ID_VARFG_SHIFT) 38 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) 39 40 #define TAMP_BOOT_MODE_BACKUP_REG_ID U(20) 41 #define TAMP_BOOT_MODE_ITF_MASK U(0x0000FF00) 42 #define TAMP_BOOT_MODE_ITF_SHIFT 8 43 44 #define TAMP_BOOT_COUNTER_REG_ID U(21) 45 46 #if defined(IMAGE_BL2) 47 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 48 STM32MP_SYSRAM_SIZE, \ 49 MT_MEMORY | \ 50 MT_RW | \ 51 MT_SECURE | \ 52 MT_EXECUTE_NEVER) 53 #elif defined(IMAGE_BL32) 54 #define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SEC_SYSRAM_BASE, \ 55 STM32MP_SEC_SYSRAM_SIZE, \ 56 MT_MEMORY | \ 57 MT_RW | \ 58 MT_SECURE | \ 59 MT_EXECUTE_NEVER) 60 61 /* Non-secure SYSRAM is used a uncached memory for SCMI message transfer */ 62 #define MAP_NS_SYSRAM MAP_REGION_FLAT(STM32MP_NS_SYSRAM_BASE, \ 63 STM32MP_NS_SYSRAM_SIZE, \ 64 MT_DEVICE | \ 65 MT_RW | \ 66 MT_NS | \ 67 MT_EXECUTE_NEVER) 68 #endif 69 70 #define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \ 71 STM32MP1_DEVICE1_SIZE, \ 72 MT_DEVICE | \ 73 MT_RW | \ 74 MT_SECURE | \ 75 MT_EXECUTE_NEVER) 76 77 #define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \ 78 STM32MP1_DEVICE2_SIZE, \ 79 MT_DEVICE | \ 80 MT_RW | \ 81 MT_SECURE | \ 82 MT_EXECUTE_NEVER) 83 84 #if defined(IMAGE_BL2) 85 static const mmap_region_t stm32mp1_mmap[] = { 86 MAP_SEC_SYSRAM, 87 MAP_DEVICE1, 88 #if STM32MP_RAW_NAND 89 MAP_DEVICE2, 90 #endif 91 {0} 92 }; 93 #endif 94 #if defined(IMAGE_BL32) 95 static const mmap_region_t stm32mp1_mmap[] = { 96 MAP_SEC_SYSRAM, 97 MAP_NS_SYSRAM, 98 MAP_DEVICE1, 99 MAP_DEVICE2, 100 {0} 101 }; 102 #endif 103 104 void configure_mmu(void) 105 { 106 mmap_add(stm32mp1_mmap); 107 init_xlat_tables(); 108 109 enable_mmu_svc_mon(0); 110 } 111 112 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 113 { 114 #if STM32MP13 115 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 116 #endif 117 #if STM32MP15 118 if (bank == GPIO_BANK_Z) { 119 return GPIOZ_BASE; 120 } 121 122 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 123 #endif 124 125 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 126 } 127 128 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 129 { 130 #if STM32MP13 131 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 132 #endif 133 #if STM32MP15 134 if (bank == GPIO_BANK_Z) { 135 return 0; 136 } 137 138 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 139 #endif 140 141 return bank * GPIO_BANK_OFFSET; 142 } 143 144 bool stm32_gpio_is_secure_at_reset(unsigned int bank) 145 { 146 #if STM32MP13 147 return true; 148 #endif 149 #if STM32MP15 150 if (bank == GPIO_BANK_Z) { 151 return true; 152 } 153 154 return false; 155 #endif 156 } 157 158 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 159 { 160 #if STM32MP13 161 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_I); 162 #endif 163 #if STM32MP15 164 if (bank == GPIO_BANK_Z) { 165 return GPIOZ; 166 } 167 168 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); 169 #endif 170 171 return GPIOA + (bank - GPIO_BANK_A); 172 } 173 174 int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank) 175 { 176 switch (bank) { 177 case GPIO_BANK_A: 178 case GPIO_BANK_B: 179 case GPIO_BANK_C: 180 case GPIO_BANK_D: 181 case GPIO_BANK_E: 182 case GPIO_BANK_F: 183 case GPIO_BANK_G: 184 case GPIO_BANK_H: 185 case GPIO_BANK_I: 186 #if STM32MP15 187 case GPIO_BANK_J: 188 case GPIO_BANK_K: 189 #endif 190 return fdt_path_offset(fdt, "/soc/pin-controller"); 191 #if STM32MP15 192 case GPIO_BANK_Z: 193 return fdt_path_offset(fdt, "/soc/pin-controller-z"); 194 #endif 195 default: 196 panic(); 197 } 198 } 199 200 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2) 201 /* 202 * UART Management 203 */ 204 static const uintptr_t stm32mp1_uart_addresses[8] = { 205 USART1_BASE, 206 USART2_BASE, 207 USART3_BASE, 208 UART4_BASE, 209 UART5_BASE, 210 USART6_BASE, 211 UART7_BASE, 212 UART8_BASE, 213 }; 214 215 uintptr_t get_uart_address(uint32_t instance_nb) 216 { 217 if ((instance_nb == 0U) || 218 (instance_nb > ARRAY_SIZE(stm32mp1_uart_addresses))) { 219 return 0U; 220 } 221 222 return stm32mp1_uart_addresses[instance_nb - 1U]; 223 } 224 #endif 225 226 #if STM32MP_USB_PROGRAMMER 227 struct gpio_bank_pin_list { 228 uint32_t bank; 229 uint32_t pin; 230 }; 231 232 static const struct gpio_bank_pin_list gpio_list[] = { 233 { /* USART2_RX: GPIOA3 */ 234 .bank = 0U, 235 .pin = 3U, 236 }, 237 { /* USART3_RX: GPIOB12 */ 238 .bank = 1U, 239 .pin = 12U, 240 }, 241 { /* UART4_RX: GPIOB2 */ 242 .bank = 1U, 243 .pin = 2U, 244 }, 245 { /* UART5_RX: GPIOB4 */ 246 .bank = 1U, 247 .pin = 5U, 248 }, 249 { /* USART6_RX: GPIOC7 */ 250 .bank = 2U, 251 .pin = 7U, 252 }, 253 { /* UART7_RX: GPIOF6 */ 254 .bank = 5U, 255 .pin = 6U, 256 }, 257 { /* UART8_RX: GPIOE0 */ 258 .bank = 4U, 259 .pin = 0U, 260 }, 261 }; 262 263 void stm32mp1_deconfigure_uart_pins(void) 264 { 265 size_t i; 266 267 for (i = 0U; i < ARRAY_SIZE(gpio_list); i++) { 268 set_gpio_reset_cfg(gpio_list[i].bank, gpio_list[i].pin); 269 } 270 } 271 #endif 272 273 uint32_t stm32mp_get_chip_version(void) 274 { 275 uint32_t version = 0U; 276 277 if (stm32mp1_dbgmcu_get_chip_version(&version) < 0) { 278 INFO("Cannot get CPU version, debug disabled\n"); 279 return 0U; 280 } 281 282 return version; 283 } 284 285 uint32_t stm32mp_get_chip_dev_id(void) 286 { 287 uint32_t dev_id; 288 289 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { 290 INFO("Use default chip ID, debug disabled\n"); 291 dev_id = STM32MP1_CHIP_ID; 292 } 293 294 return dev_id; 295 } 296 297 static uint32_t get_part_number(void) 298 { 299 static uint32_t part_number; 300 301 if (part_number != 0U) { 302 return part_number; 303 } 304 305 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 306 panic(); 307 } 308 309 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >> 310 PART_NUMBER_OTP_PART_SHIFT; 311 312 part_number |= stm32mp_get_chip_dev_id() << 16; 313 314 return part_number; 315 } 316 317 static uint32_t get_cpu_package(void) 318 { 319 uint32_t package; 320 321 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 322 panic(); 323 } 324 325 package = (package & PACKAGE_OTP_PKG_MASK) >> 326 PACKAGE_OTP_PKG_SHIFT; 327 328 return package; 329 } 330 331 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 332 { 333 char *cpu_s, *cpu_r, *pkg; 334 335 /* MPUs Part Numbers */ 336 switch (get_part_number()) { 337 case STM32MP157C_PART_NB: 338 cpu_s = "157C"; 339 break; 340 case STM32MP157A_PART_NB: 341 cpu_s = "157A"; 342 break; 343 case STM32MP153C_PART_NB: 344 cpu_s = "153C"; 345 break; 346 case STM32MP153A_PART_NB: 347 cpu_s = "153A"; 348 break; 349 case STM32MP151C_PART_NB: 350 cpu_s = "151C"; 351 break; 352 case STM32MP151A_PART_NB: 353 cpu_s = "151A"; 354 break; 355 case STM32MP157F_PART_NB: 356 cpu_s = "157F"; 357 break; 358 case STM32MP157D_PART_NB: 359 cpu_s = "157D"; 360 break; 361 case STM32MP153F_PART_NB: 362 cpu_s = "153F"; 363 break; 364 case STM32MP153D_PART_NB: 365 cpu_s = "153D"; 366 break; 367 case STM32MP151F_PART_NB: 368 cpu_s = "151F"; 369 break; 370 case STM32MP151D_PART_NB: 371 cpu_s = "151D"; 372 break; 373 default: 374 cpu_s = "????"; 375 break; 376 } 377 378 /* Package */ 379 switch (get_cpu_package()) { 380 case PKG_AA_LFBGA448: 381 pkg = "AA"; 382 break; 383 case PKG_AB_LFBGA354: 384 pkg = "AB"; 385 break; 386 case PKG_AC_TFBGA361: 387 pkg = "AC"; 388 break; 389 case PKG_AD_TFBGA257: 390 pkg = "AD"; 391 break; 392 default: 393 pkg = "??"; 394 break; 395 } 396 397 /* REVISION */ 398 switch (stm32mp_get_chip_version()) { 399 case STM32MP1_REV_B: 400 cpu_r = "B"; 401 break; 402 case STM32MP1_REV_Z: 403 cpu_r = "Z"; 404 break; 405 default: 406 cpu_r = "?"; 407 break; 408 } 409 410 snprintf(name, STM32_SOC_NAME_SIZE, 411 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 412 } 413 414 void stm32mp_print_cpuinfo(void) 415 { 416 char name[STM32_SOC_NAME_SIZE]; 417 418 stm32mp_get_soc_name(name); 419 NOTICE("CPU: %s\n", name); 420 } 421 422 void stm32mp_print_boardinfo(void) 423 { 424 uint32_t board_id = 0; 425 426 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 427 return; 428 } 429 430 if (board_id != 0U) { 431 char rev[2]; 432 433 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; 434 rev[1] = '\0'; 435 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", 436 BOARD_ID2NB(board_id), 437 BOARD_ID2VARCPN(board_id), 438 BOARD_ID2VARFG(board_id), 439 rev, 440 BOARD_ID2BOM(board_id)); 441 } 442 } 443 444 /* Return true when SoC provides a single Cortex-A7 core, and false otherwise */ 445 bool stm32mp_is_single_core(void) 446 { 447 #if STM32MP13 448 return true; 449 #endif 450 #if STM32MP15 451 bool single_core = false; 452 453 switch (get_part_number()) { 454 case STM32MP151A_PART_NB: 455 case STM32MP151C_PART_NB: 456 case STM32MP151D_PART_NB: 457 case STM32MP151F_PART_NB: 458 single_core = true; 459 break; 460 default: 461 break; 462 } 463 464 return single_core; 465 #endif 466 } 467 468 /* Return true when device is in closed state */ 469 bool stm32mp_is_closed_device(void) 470 { 471 uint32_t value; 472 473 if (stm32_get_otp_value(CFG0_OTP, &value) != 0) { 474 return true; 475 } 476 477 return (value & CFG0_CLOSED_DEVICE) == CFG0_CLOSED_DEVICE; 478 } 479 480 /* Return true when device supports secure boot */ 481 bool stm32mp_is_auth_supported(void) 482 { 483 bool supported = false; 484 485 switch (get_part_number()) { 486 case STM32MP151C_PART_NB: 487 case STM32MP151F_PART_NB: 488 case STM32MP153C_PART_NB: 489 case STM32MP153F_PART_NB: 490 case STM32MP157C_PART_NB: 491 case STM32MP157F_PART_NB: 492 supported = true; 493 break; 494 default: 495 break; 496 } 497 498 return supported; 499 } 500 501 uint32_t stm32_iwdg_get_instance(uintptr_t base) 502 { 503 switch (base) { 504 case IWDG1_BASE: 505 return IWDG1_INST; 506 case IWDG2_BASE: 507 return IWDG2_INST; 508 default: 509 panic(); 510 } 511 } 512 513 uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst) 514 { 515 uint32_t iwdg_cfg = 0U; 516 uint32_t otp_value; 517 518 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 519 panic(); 520 } 521 522 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) { 523 iwdg_cfg |= IWDG_HW_ENABLED; 524 } 525 526 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) { 527 iwdg_cfg |= IWDG_DISABLE_ON_STOP; 528 } 529 530 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) { 531 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY; 532 } 533 534 return iwdg_cfg; 535 } 536 537 #if defined(IMAGE_BL2) 538 uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags) 539 { 540 uint32_t otp_value; 541 uint32_t otp; 542 uint32_t result; 543 544 if (stm32_get_otp_index(HW2_OTP, &otp, NULL) != 0) { 545 panic(); 546 } 547 548 if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) { 549 panic(); 550 } 551 552 if ((flags & IWDG_DISABLE_ON_STOP) != 0) { 553 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS); 554 } 555 556 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0) { 557 otp_value |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS); 558 } 559 560 result = bsec_write_otp(otp_value, otp); 561 if (result != BSEC_OK) { 562 return result; 563 } 564 565 /* Sticky lock OTP_IWDG (read and write) */ 566 if ((bsec_set_sr_lock(otp) != BSEC_OK) || 567 (bsec_set_sw_lock(otp) != BSEC_OK)) { 568 return BSEC_LOCK_FAIL; 569 } 570 571 return BSEC_OK; 572 } 573 #endif 574 575 #if STM32MP_USE_STM32IMAGE 576 /* Get the non-secure DDR size */ 577 uint32_t stm32mp_get_ddr_ns_size(void) 578 { 579 static uint32_t ddr_ns_size; 580 uint32_t ddr_size; 581 582 if (ddr_ns_size != 0U) { 583 return ddr_ns_size; 584 } 585 586 ddr_size = dt_get_ddr_size(); 587 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) || 588 (ddr_size > STM32MP_DDR_MAX_SIZE)) { 589 panic(); 590 } 591 592 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE); 593 594 return ddr_ns_size; 595 } 596 #endif /* STM32MP_USE_STM32IMAGE */ 597 598 void stm32_save_boot_interface(uint32_t interface, uint32_t instance) 599 { 600 uintptr_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 601 602 clk_enable(RTCAPB); 603 604 mmio_clrsetbits_32(bkpr_itf_idx, 605 TAMP_BOOT_MODE_ITF_MASK, 606 ((interface << 4) | (instance & 0xFU)) << 607 TAMP_BOOT_MODE_ITF_SHIFT); 608 609 clk_disable(RTCAPB); 610 } 611 612 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance) 613 { 614 static uint32_t itf; 615 616 if (itf == 0U) { 617 uintptr_t bkpr = tamp_bkpr(TAMP_BOOT_MODE_BACKUP_REG_ID); 618 619 clk_enable(RTCAPB); 620 621 itf = (mmio_read_32(bkpr) & TAMP_BOOT_MODE_ITF_MASK) >> 622 TAMP_BOOT_MODE_ITF_SHIFT; 623 624 clk_disable(RTCAPB); 625 } 626 627 *interface = itf >> 4; 628 *instance = itf & 0xFU; 629 } 630 631 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 632 void stm32mp1_fwu_set_boot_idx(void) 633 { 634 clk_enable(RTCAPB); 635 mmio_write_32(tamp_bkpr(TAMP_BOOT_COUNTER_REG_ID), 636 plat_fwu_get_boot_idx()); 637 clk_disable(RTCAPB); 638 } 639 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 640