Merge "fix(fvp): fix NULL pointer dereference issue" into integration

feat(brbe): add BRBE support for NS world

This patch enables access to the branch record buffer control registers
in non-secure EL2 and EL1 using the new build option ENABLE_BRBE_FOR_NS.
It is disab

feat(brbe): add BRBE support for NS world

This patch enables access to the branch record buffer control registers
in non-secure EL2 and EL1 using the new build option ENABLE_BRBE_FOR_NS.
It is disabled for all secure world, and cannot be used with ENABLE_RME.

This option is disabled by default, however, the FVP platform makefile
enables it for FVP builds.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I576a49d446a8a73286ea6417c16bd0b8de71fca0

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feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC

SMPLSEL and DRVSEL values need to updated in
DWMMC for the IP to work correctly. This apply
on Stratix 10 device only.

Signed-off-by: Lo

feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC

SMPLSEL and DRVSEL values need to updated in
DWMMC for the IP to work correctly. This apply
on Stratix 10 device only.

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibd799a65890690682e27e4cbbc85e83ea03d51fc

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feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge

This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properl

feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge

This adds F2S and S2F bridge enable, disable and reset
sequence to enable, disable and reset properly the bridges
in SMC call or during reset.

The reset is also maskable as the SMC from uboot can
pass in the bridge mask when requesting for bridge
enable or disable.

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie144518c591664ef880016c9b3706968411bbf21

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Merge "fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS)" into integration

fix(fvp): fix NULL pointer dereference issue

Fixed below NULL pointer dereference issue reported by coverity scan
by asserting the hw_config_info is not NULL.

*** CID 378361: Null pointer derefere

fix(fvp): fix NULL pointer dereference issue

Fixed below NULL pointer dereference issue reported by coverity scan
by asserting the hw_config_info is not NULL.

*** CID 378361: Null pointer dereferences (NULL_RETURNS)
/plat/arm/board/fvp/fvp_bl2_setup.c: 84 in plat_get_next_bl_params()
78
79 /* To retrieve actual size of the HW_CONFIG */
80 param_node = get_bl_mem_params_node(HW_CONFIG_ID);
81 assert(param_node != NULL);
82
83 /* Copy HW config from Secure address to NS address */
>>> CID 378361: Null pointer dereferences (NULL_RETURNS)
>>> Dereferencing "hw_config_info", which is known to be "NULL".
84 memcpy((void *)hw_config_info->ns_config_addr,
85 (void *)hw_config_info->config_addr,
86 (size_t)param_node->image_info.image_size);

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: Iaf584044cfc3b2583862bcc1be825966eaffd38e

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feat(plat/fvp): add EL3 SPMC #defines

Introduce additional #defines for running with the EL3
SPMC on the FVP.

The increase in xlat tables has been chosen to allow
the test cases to complete success

feat(plat/fvp): add EL3 SPMC #defines

Introduce additional #defines for running with the EL3
SPMC on the FVP.

The increase in xlat tables has been chosen to allow
the test cases to complete successfully and may need
adjusting depending on the desired usecase.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I7f44344ff8b74ae8907d53ebb652ff8def2d2562

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test(plat/fvp/lsp): add example logical partition

Add an example logical partition to the FVP platform that
simply prints and echos the contents of a direct request
with the appropriate direct respo

test(plat/fvp/lsp): add example logical partition

Add an example logical partition to the FVP platform that
simply prints and echos the contents of a direct request
with the appropriate direct response.

Change-Id: Ib2052c9a63a74830e5e83bd8c128c5f9b0d94658
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>

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Merge changes from topic "mp/delete_platforms" into integration

* changes:
refactor(mt6795): remove mediatek's mt6795 platform
refactor(sgm775): remove Arm sgm775 platform

fix(sptool): update Optee FF-A manifest

Change the OPTEE FF-A manifest to comply with changes to the sp pkg [1].
The sptool packs the image at the default offset of 0x4000, if it is not
provided in

fix(sptool): update Optee FF-A manifest

Change the OPTEE FF-A manifest to comply with changes to the sp pkg [1].
The sptool packs the image at the default offset of 0x4000, if it is not
provided in the arguments.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/14507

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I647950410114f7fc24926696212bb7f8101390ac

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refactor(mt6795): remove mediatek's mt6795 platform

Mediatek's mt6795 platform was deprecated in 2.5 release and as per [1]
a platform which has been marked deprecated should be removed from repo
af

refactor(mt6795): remove mediatek's mt6795 platform

Mediatek's mt6795 platform was deprecated in 2.5 release and as per [1]
a platform which has been marked deprecated should be removed from repo
after 2 release cycle.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/plat/deprecated.html?highlight=deprecated

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic427a3071316a13f34a726a1eb086b679e1671a1

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refactor(sgm775): remove Arm sgm775 platform

Arm's sgm775 platform was deprecated in 2.5 release and as per [1] a
platform which has been marked deprecated should be removed from repo
after 2 releas

refactor(sgm775): remove Arm sgm775 platform

Arm's sgm775 platform was deprecated in 2.5 release and as per [1] a
platform which has been marked deprecated should be removed from repo
after 2 release cycle.

[1] https://trustedfirmware-a.readthedocs.io/en/latest/plat/deprecated.html?highlight=deprecated

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I3cce6f330a1def725188eefd558bd0e4ec559725

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feat(allwinner): add SMCCC SOCID support

The Allwinner SID device holds a 16-bit SoC identifier, which we already
use in our code.

Export this number through the generic SMCCC SOCID interface, to a

feat(allwinner): add SMCCC SOCID support

The Allwinner SID device holds a 16-bit SoC identifier, which we already
use in our code.

Export this number through the generic SMCCC SOCID interface, to allow
an architectural identification of an Allwinner SoC. This enables access
to this information from non-secure world, simplifies generic drivers
(ACPI comes to mind), and gives easy and precise access to the SoC ID
from userland in OSes like Linux.

Change-Id: I91753046b2ae5408ca7bc0b864fcd97d24c8267c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "allwinner-idle" into integration

* changes:
feat(allwinner): provide CPU idle states to the rich OS
feat(allwinner): simplify CPU_SUSPEND power state encoding
feat(al

Merge changes from topic "allwinner-idle" into integration

* changes:
feat(allwinner): provide CPU idle states to the rich OS
feat(allwinner): simplify CPU_SUSPEND power state encoding
feat(allwinner): choose PSCI states to avoid translation
feat(fdt): add the ability to supply idle state information
fix(allwinner): improve DTB patching error handling
refactor(allwinner): patch the DTB after setting up PSCI
refactor(allwinner): move DTB change code into allwinner/common

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Merge changes from topic "refactor-hw-config-load" into integration

* changes:
docs(fvp): update loading addresses of HW_CONFIG
docs(fconf): update device tree binding for FCONF
feat(fvp): upd

Merge changes from topic "refactor-hw-config-load" into integration

* changes:
docs(fvp): update loading addresses of HW_CONFIG
docs(fconf): update device tree binding for FCONF
feat(fvp): update HW_CONFIG DT loading mechanism
refactor(st): update set_config_info function call
refactor(fvp_r): update set_config_info function call
refactor(arm): update set_config_info function call
feat(fconf): add NS load address in configuration DTB nodes

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feat(xilinx): add SPP/EMU platform support for versal

This patch adds SPP/EMU platform support for Xilinx Versal and
also updating the documentation.

Signed-off-by: Venkatesh Yadav Abbarapu <venkat

feat(xilinx): add SPP/EMU platform support for versal

This patch adds SPP/EMU platform support for Xilinx Versal and
also updating the documentation.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ibdadec4d00cd33ea32332299e7a00de31dc9d60b

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fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS)

This patch is to add size checking to make sure that
each certificate and encryption/decryption request
are 4-byte alig

fix(intel): reject non 4-byte align request size for FPGA Crypto Service (FCS)

This patch is to add size checking to make sure that
each certificate and encryption/decryption request
are 4-byte align as this driver is expecting. Unaligned
size may indicate invalid/corrupted request hence will
be rejected.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ib6f97849ec470e45679c5adc4fbfa3afd10eda90

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fix(zynqmp): update the log message to verbose

Changing the log message from notice to verbose, to save some space
and that leads to successfull compilation.

Signed-off-by: Venkatesh Yadav Abbarapu

fix(zynqmp): update the log message to verbose

Changing the log message from notice to verbose, to save some space
and that leads to successfull compilation.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Iee5a808febf211464eb8ba6f0377f79378333f5d

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Merge "feat(smmu): configure SMMU Root interface" into integration

Merge changes I80661161,I82c1fa93,I018ccbb9,Ibc23734d,I97406abe, ... into integration

* changes:
feat(intel): add SMC support for HWMON voltage and temp sensor
feat(intel): add SMC support for G

Merge changes I80661161,I82c1fa93,I018ccbb9,Ibc23734d,I97406abe, ... into integration

* changes:
feat(intel): add SMC support for HWMON voltage and temp sensor
feat(intel): add SMC support for Get USERCODE
fix(intel): extend SDM command to return the SDM firmware version
feat(intel): add SMC for enquiring firmware version
fix(intel): configuration status based on start request
fix(intel): bit-wise configuration flag handling
fix(intel): get config status OK status
fix(intel): use macro as return value
fix(intel): fix fpga config write return mechanism
feat(intel): add SiP service for DCMF status
feat(intel): add RSU 'Max Retry' SiP SMC services
feat(intel): enable SMC SoC FPGA bridges enable/disable
feat(intel): add SMC/PSCI services for DCMF version support
feat(intel): allow to access all register addresses if DEBUG=1
fix(intel): modify how configuration type is handled
feat(intel): support SiP SVC version
feat(intel): enable firewall for OCRAM in BL31
feat(intel): create source file for firewall configuration
fix(intel): refactor NOC header

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feat(smmu): configure SMMU Root interface

This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions

feat(smmu): configure SMMU Root interface

This change performs a basic configuration of the SMMU root registers
interface on an RME enabled system. This permits enabling GPC checks
for transactions originated from a non-secure or secure device upstream
to an SMMU. It re-uses the boot time GPT base address and configuration
programmed on the PE.
The root register file offset is platform dependent and has to be
supplied on a model command line.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4f889be6b7afc2afb4d1d147c5c1c3ea68f32e07

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Merge "feat(qemu): add support for measured boot" into integration

feat(intel): add SMC support for HWMON voltage and temp sensor

Add support to read temperature and voltage using SMC command

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-by

feat(intel): add SMC support for HWMON voltage and temp sensor

Add support to read temperature and voltage using SMC command

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I806611610043906b720b5096728a5deb5d652b1d

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feat(intel): add SMC support for Get USERCODE

This patch adds SMC support for enquiring FPGA's User Code.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.

feat(intel): add SMC support for Get USERCODE

This patch adds SMC support for enquiring FPGA's User Code.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I82c1fa9390b6f7509b2284d51e199fb8b6a9b1ad

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fix(intel): extend SDM command to return the SDM firmware version

Updates intel_smc_fw_version function to read SDM
firmware version in major/minor ACDS release number.
Update CONFIG_STATUS Response

fix(intel): extend SDM command to return the SDM firmware version

Updates intel_smc_fw_version function to read SDM
firmware version in major/minor ACDS release number.
Update CONFIG_STATUS Response Data [1] bit0-23.

Return INTEL_SIP_SMC_STATUS_ERROR if unexpected
firmware version is being retrieved.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I018ccbb961786a75dc6eb873b0f232e71341e1d2

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