feat(imx8mq): enable dram dvfs support on imx8mq

Enable DRAM DVFS support on i.MX8MQ.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id72c5eb9625936052ec51e5a52d9d31175ed1b1b

feat(imx8m): use non-fast wakeup stop mode for system suspend

Use non-fast wakeup stop mode for system suspend support, so
the SOC can enter DSM mode by default.

Signed-off-by: Jacky Bai <ping.bai@

feat(imx8m): use non-fast wakeup stop mode for system suspend

Use non-fast wakeup stop mode for system suspend support, so
the SOC can enter DSM mode by default.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I37828d4e66ee2ebd48e7adca054b93c520cb2c82

show more ...

feat(imx8mq): correct the slot ack setting for STOP mode

A53 core's power up ack need to be used when system resume
from DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I47fb33c058

feat(imx8mq): correct the slot ack setting for STOP mode

A53 core's power up ack need to be used when system resume
from DSM mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I47fb33c0582ae5f483ffaa887f95e27bd47875f7

show more ...

feat(imx8mq): add anamix pll override setting for DSM mode

Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.

Signed-off-by: Jack

feat(imx8mq): add anamix pll override setting for DSM mode

Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ibe954bc7c4a7b453ace13f8e4b6a335e6d4856c3

show more ...

feat(imx8mq): add workaround code for ERR11171 on imx8mq

This new workaround takes advantage of the per core IMR
registers in GPC in order to unmask the IRQ0, still generated
by the 12bit in IOMUX_G

feat(imx8mq): add workaround code for ERR11171 on imx8mq

This new workaround takes advantage of the per core IMR
registers in GPC in order to unmask the IRQ0, still generated
by the 12bit in IOMUX_GPR register (which now remains always set),
so it can only wake up one core at the time.Also, this entire
workaround has now been moved here in TF-A, allowing the kernel
side to be minimal.

Another advantage this workaround brings is the removal of the
50us delay (which was necessary before in gic_raise_softirq in
kernel) by allowing the core that is waking up to mask his own
IRQ0 in the suspend finish callback.

One important change here is the way the cores are woken up in
dram_dvfs_handler. Since the wake up mechanism has changed from
asserting the 12th bit in IOMUX_GPR and leaving the IMR1 1st bit
on for each core to exactly the reverse, that is, leaving the
IOMUX_GPR 12th bit always set and then masking/unmasking the IMR1
1st bit for each independent core, we need to use the imx_gpc_core_wake
to wake up the cores.

Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off)
from kernel(gic_raise_softirq), since the new cpuidle workaround
does not need it in order to clean the IOMUX_GPC 12bit. For now,
the udelay seems to be still needed in order to delay the affinity
info OFF for the dying core. This is something that needs further
investigation.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I9f17ff6fc3452b8225a50b232964712aafeab78a

show more ...

feat(imx8mq): add the dram retention support for imx8mq

Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be co

feat(imx8mq): add the dram retention support for imx8mq

Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be copied from dram into ocram.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Id8264c342fd62e297b1969cba5ed505450c78a25

show more ...

feat(imx8mq): add version for B2

iMX8MQ B2 chip uses same OCOTP magic value with B1. So
read the ROM version to distinguish it with B1.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <

feat(imx8mq): add version for B2

iMX8MQ B2 chip uses same OCOTP magic value with B1. So
read the ROM version to distinguish it with B1.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I3e6865922deeb66816a0dddb49d986405e802b6f

show more ...

fix(imx8m): backup mr12/14 value from lpddr4 chip

Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.

Signed-off-by: Jacky Bai <ping.bai@nxp.co

fix(imx8m): backup mr12/14 value from lpddr4 chip

Backup the mr12/14 value as the actual value used is not the
one we configured in the ddrc config timing.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: If04733b34a3b4c080828bb7c82e83f0badbeaafd

show more ...

Merge "fix(rme): update sample platform attestation token" into integration

fix(pauth): make pauth_helpers linking generic

Pauth is a generic Arm feature that can be enabled on any platform that
implements it. It only needs a platform specific key generation hook. As
such,

fix(pauth): make pauth_helpers linking generic

Pauth is a generic Arm feature that can be enabled on any platform that
implements it. It only needs a platform specific key generation hook. As
such, the generic Pauth enablement can be included in the generic build.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibf32f79addab3515214594bb8d7168151b450f59

show more ...

Merge changes from topic "feat_state_part2" into integration

* changes:
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
refactor(t

Merge changes from topic "feat_state_part2" into integration

* changes:
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED
fix(cpufeat): context-switch: move FGT availability check to callers
feat(cpufeat): extend check_feature() to deal with min/max
refactor(cpufeat): wrap CPU ID register field isolation

show more ...

fix(imx8m): add ddr4 dvfs sw workaround for ERR050712

APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring

When performing a software driven MR access, t

fix(imx8m): add ddr4 dvfs sw workaround for ERR050712

APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring

When performing a software driven MR access, the following
sequence must be done automatically before performing other
APB register accesses:

1. Set MRCTRL0.mr_wr=1
2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
3. Check for MRSTAT.mr_wr_busy=0 again (for the second time),
if not, go to step (2).

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ie26e08bcc83d3ed4844ed04a853162308dcdccd0

show more ...

fix(imx8m): fix coverity out of bound access issue

Fix the out of bound access to the rank setting array.

Fix Coverity issue:

CID 6474575: Out-of-bounds access (OVERRUN)
CID 11014855: Unused value

fix(imx8m): fix coverity out of bound access issue

Fix the out of bound access to the rank setting array.

Fix Coverity issue:

CID 6474575: Out-of-bounds access (OVERRUN)
CID 11014855: Unused value (UNUSED_VALUE)

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I5d9ef90f1479e5d46d1b6c8693a27e3abd614766

show more ...

fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0

It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's

fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0

It seems the DRAM APB clock root slice can NOT work normally
if the PLLs is power down in DSM mode. So update this clock
slice's setting explicitly to make it work. This piece of code
is there for a long while on previous release, so just add
it back to align with previous flow.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Change-Id: I113069494074194e116fdb1229052d2956bf90ea

show more ...

feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3200mts & 4000mts.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4

feat(imx8m): add more dram pll setting

Add DRAM PLL frequency setting for 3200mts & 4000mts.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4b0609f9e7c0f35d75a26ec9ccebec77b3dbe68f

show more ...

fix(imx8m): fix the current fsp init

The dfimisc reg value should be shift right 8 bit to
get the current fsp.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.

fix(imx8m): fix the current fsp init

The dfimisc reg value should be shift right 8 bit to
get the current fsp.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Change-Id: I4c8c166bc3ad4cc1376961cbf47631c68b5900cc

show more ...

fix(imx8m): fix the rank to rank space issue

update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed

fix(imx8m): fix the rank to rank space issue

update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I0fab18cdc378fda760daa0f89c4dd84eb46f7e11

show more ...

refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED

At the moment we only support FEAT_TRF to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detecti

refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED

At the moment we only support FEAT_TRF to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_TRF_FOR_NS=2), by splitting
is_feat_trf_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access TRF related registers.
Also move the context saving code from assembly to C, and use the new
is_feat_trf_supported() function to guard its execution.

The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_TRF is an ARMv8.4 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.

Change-Id: Ia97b01adbe24970a4d837afd463dc5506b7295a3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED

At the moment we only support FEAT_BRBE to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime dete

refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED

At the moment we only support FEAT_BRBE to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_BRBE_FOR_NS=2), by splitting
is_feat_brbe_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access BRBE related registers.

The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_BRBE is an ARMv9 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.

Change-Id: I5f2e2c9648300f65f0fa9a5f8e2f34e73529d053
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED

At the moment we only support FEAT_TRBE to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime dete

refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED

At the moment we only support FEAT_TRBE to be either unconditionally
compiled in, or to be not supported at all.

Add support for runtime detection (ENABLE_TRBE_FOR_NS=2), by splitting
is_feat_trbe_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access TRBE related registers.

The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_TRBE is an ARMv9 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.

Change-Id: Iee7f88ea930119049543a8a4a105389997e7692c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

Merge changes from topic "mbedtls3_support" into integration

* changes:
feat(stm32mp1): add mbedtls-3.3 support config
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
style(crypto): add b

Merge changes from topic "mbedtls3_support" into integration

* changes:
feat(stm32mp1): add mbedtls-3.3 support config
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
style(crypto): add braces for if statement
feat(fvp): increase BL1_RW and BL2 size
feat(mbedtls): add support for mbedtls-3.3
refactor(crypto): avoid using struct mbedtls_pk_rsassa_pss_options
refactor(mbedtls): avoid including MBEDTLS_CONFIG_FILE

show more ...

feat(stm32mp1): add mbedtls-3.3 support config

Add stm32mp1_mbedtls_config-3.h config file for stm32mp1 builds with
mbedtls-3.3

Change-Id: I4581cb0ea7b2c7022e71aefd7ff05ee3a72f5883
Signed-off-by: G

feat(stm32mp1): add mbedtls-3.3 support config

Add stm32mp1_mbedtls_config-3.h config file for stm32mp1 builds with
mbedtls-3.3

Change-Id: I4581cb0ea7b2c7022e71aefd7ff05ee3a72f5883
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

revert(zynqmp): remove EM SMC handler

EM support was out of SMC SIP range that's why has been moved to SIP
range 0x3000 by commit acbae3998bd8 ("fix(zynqmp): move EM SMC range
to SIP range").
But af

revert(zynqmp): remove EM SMC handler

EM support was out of SMC SIP range that's why has been moved to SIP
range 0x3000 by commit acbae3998bd8 ("fix(zynqmp): move EM SMC range
to SIP range").
But after another investigation was found that this interface has no
user in any our SW and likely never adopted by anybody else. That's
why simply remove it. If there is any user it can be added back but
as TF-A size is challenging removing unused code is very welcome.
Origin code was added by commit 504925f99da0 ("xilinx: zynqmp: Add
support for Error Management").

Change-Id: I2d9222d7dde507400893e06f7f12e1713ce6bc9a
Signed-off-by: Michal Simek <michal.simek@amd.com>

show more ...

fix(imx8m): fix the dfiphymaster setting after dvfs

the dfi phy master setting need to be save/restore to make
sure it aligned with the initial config.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
R

fix(imx8m): fix the dfiphymaster setting after dvfs

the dfi phy master setting need to be save/restore to make
sure it aligned with the initial config.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: I4f572b9aff9cc47a6c28524ce0fe03cdc66b88a1

show more ...

feat(imx8m): update the ddr4 dvfs flow to include ddr3l support

the DDR3L & DDR4 can share same piece of code for DDR frequency scaling.
So update the ddr4 dvfs flow to support DDR3L too.

Signed-of

feat(imx8m): update the ddr4 dvfs flow to include ddr3l support

the DDR3L & DDR4 can share same piece of code for DDR frequency scaling.
So update the ddr4 dvfs flow to support DDR3L too.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Change-Id: Ifc6981f05ed8a4e399adad97690197a9680f554d

show more ...