fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF

This flag just needs to be defined, and does not need to have a boolean
value. Remove it from the assert_booleans check.

Signed-off-by: Yann

fix(stm32mp1): remove boolean check on PLAT_TBBR_IMG_DEF

This flag just needs to be defined, and does not need to have a boolean
value. Remove it from the assert_booleans check.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I4e4c9ae1e5003ca2cf7c0c0e31d1561d032937c8

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feat(fvp): define ns memory in the SPMC manifest

The SPMC (Hafnium) looks for secure and non-secure ranges
in its manifest.
Those relate with ranges that can be used by SPs in their
FF-A manifests.

feat(fvp): define ns memory in the SPMC manifest

The SPMC (Hafnium) looks for secure and non-secure ranges
in its manifest.
Those relate with ranges that can be used by SPs in their
FF-A manifests.
The NS memory that is not used by SPs will be assigned
to the NWd, for it to share memory with SPs as needed.
Thus, this limits the memory the NWd can share with SPs,
to prevent NWD VMs from sharing memory that belongs
to other critical components.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Iad03eb138a57068fbb18c53141bdf6bf9c171b28

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Merge "feat(xilinx): sync copyright format" into integration

Merge "build: deprecate Arm rde1edge" into integration

Merge "fix(sme): disable SME for SPD=spmd" into integration

Merge changes Ia1142b31,I424f1cde into integration

* changes:
fix(tc): enable the execution of both platform tests
fix(tc): update the name of mbedtls config header

Merge "refactor(fiptool): move plat_fiptool.mk to tools" into integration

feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder fo

feat(spmd): introduce platform handler for Group0 interrupt

This patch introduces a handler for FVP platform to triage Group0
secure interrupts. Currently, it is empty but serves as a
placeholder for future Group0 interrupt sources.

Moreover, this patch also provides a dummy implementation of the
above mentioned platform hook for QEMU, corstone100, n1sdp and
hikey960 ports.

Change-Id: I01d3451408f47ac313b0af74046cce89f89b85bb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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fix(tegra): remove dependency on CPU registers to get boot parameters

Commit 3e14df6f6 removed the code to clear the CPU registers X0 - X3,
which affected the Tegra platforms. Tegra platforms rely o

fix(tegra): remove dependency on CPU registers to get boot parameters

Commit 3e14df6f6 removed the code to clear the CPU registers X0 - X3,
which affected the Tegra platforms. Tegra platforms rely on the boot
parameters passed through custom mechanisms and do not use these
general purpose registers, but maintained sanity checks to support
legacy bootloaders. These sanity checks went out of sync due to the
code cleanup from bl31_entrypoint().

This patch removes the checks and calls the SOC specific handlers to
retrieve the boot parameters.

Change-Id: I0cf4d9c0370c33ff7715b48592b6bc0602f3c93e
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "feat(fvp): introduce PLATFORM_TEST_EA_FFH config" into integration

fix(sme): disable SME for SPD=spmd

SPMD is not compatible with ENABLE_SME_FOR_NS.
Hence disable SME when SPD=spmd

Change-Id: I8bcf2493819718732563f9db69f7186ac7437637
Signed-off-by: Jayanth Dodderi

fix(sme): disable SME for SPD=spmd

SPMD is not compatible with ENABLE_SME_FOR_NS.
Hence disable SME when SPD=spmd

Change-Id: I8bcf2493819718732563f9db69f7186ac7437637
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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feat(fvp): introduce PLATFORM_TEST_EA_FFH config

FVP currently does not have proper handler to do Firmware First Handling
(FFH) of lower EL External aborts and it ends up in EL3 panic.

To test the

feat(fvp): introduce PLATFORM_TEST_EA_FFH config

FVP currently does not have proper handler to do Firmware First Handling
(FFH) of lower EL External aborts and it ends up in EL3 panic.

To test the scenarios sensibly we need a proper handling when the FVP is
under test so that we do not change the default behavior.

Introduce PLATFORM_TEST_EA_FFH config which will be enabled in CI
scripts and implement a proper handling for Sync EA and SErrors from
lower EL.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib130154206b17f72c49c9f07de2d92f35a97ab0b

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Merge "feat(sme): enable SME2 functionality for NS world" into integration

fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <mar

fix(qemu-sbsa): enable FGT

QEMU 7.2+ has FEAT_FGT support added to 'max' cpu.

So let's enable it to make Debian 'bookworm' kernel boot on sbsa-ref/max setup.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I49fb3e742b69ce7be5666e0144525dde21a68238

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chore(bl1): remove redundant bl1_arch_next_el_setup

bl1_arch_next_el_setup has no references anywhere in TF-A. Remove it as
it is redundant

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

chore(bl1): remove redundant bl1_arch_next_el_setup

bl1_arch_next_el_setup has no references anywhere in TF-A. Remove it as
it is redundant

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ice2997f33c318390883347acdd03dc6755f87ea5

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Merge "build(fvp): reduce the number of cpu libraries included by default" into integration

Merge "style(xilinx): fix AMD copyright format" into integration

feat(sme): enable SME2 functionality for NS world

FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations ef

feat(sme): enable SME2 functionality for NS world

FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations efficiently, but also provides
outer-product instructions to accelerate matrix operations.
It affords instructions for multi-vector operations.
Further, it adds an 512 bit architectural register ZT0.

This patch implements all the changes introduced with FEAT_SME2
to ensure that the instructions are allowed to access ZT0
register from Non-secure lower exception levels.

Additionally, it adds support to ensure FEAT_SME2 is aligned
with the existing FEATURE DETECTION mechanism, and documented.

Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(tc): enable the execution of both platform tests

The C preprocessor cannot compare defines against strings.
Such an expression is always evaluated to be true. Therefore,
its usage in a condition

fix(tc): enable the execution of both platform tests

The C preprocessor cannot compare defines against strings.
Such an expression is always evaluated to be true. Therefore,
its usage in a conditional expression results that always the
first branch is taken. Other branches cannot be reached by
any configuration value. The fix removes this string comparison
and instead it introduces distinct defines for all the cases.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ia1142b31b6778686c74e1e882fe4604fe3b6501d

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fix(tc): update the name of mbedtls config header

Recently mbedtls_cofig.h was renamed to:
- mbedtls_config-2.h
- mbedtls_config-3.h

Modify the include order to resolve the
static check failure i

fix(tc): update the name of mbedtls config header

Recently mbedtls_cofig.h was renamed to:
- mbedtls_config-2.h
- mbedtls_config-3.h

Modify the include order to resolve the
static check failure in the CI.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I424f1cde199397b8df780a9514f1042e601c6502

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feat(tegra): implement 'pwr_domain_off_early' handler

This patch implements the pwr_domain_off_early handler for
Tegra platforms.

Powering off the boot core on some Tegra platforms is not
allowed a

feat(tegra): implement 'pwr_domain_off_early' handler

This patch implements the pwr_domain_off_early handler for
Tegra platforms.

Powering off the boot core on some Tegra platforms is not
allowed and the SOC specific helper functions for Tegra194,
Tegra210 and Tegra186 implement this restriction.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I9d06e0eee12314764adb0422e023a5bec6ed9c1e

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Merge changes from topic "ti-sci-cleanup" into integration

* changes:
feat(ti): synchronize access to secure proxy threads
refactor(ti): remove inline directive from ti_sci and sec_proxy drivers

Merge changes from topic "ti-sci-cleanup" into integration

* changes:
feat(ti): synchronize access to secure proxy threads
refactor(ti): remove inline directive from ti_sci and sec_proxy drivers
refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response
feat(ti): add sub and patch version number support

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feat(allwinner): add support for Allwinner T507 SoC

The Allwinner T507 SoC is using the same die as the H616, but in a
different package. On top of this, there is at least one different die
revision

feat(allwinner): add support for Allwinner T507 SoC

The Allwinner T507 SoC is using the same die as the H616, but in a
different package. On top of this, there is at least one different die
revision out there, which uses a different CPU cluster control block.
The same die revision has been spotted in some, but not all, H313 SoCs.

Apart from that IP block, the rest of the SoC seems the same, so we can
support them using the existing H616 port. The die revision can be
auto-detected, so there is no extra build option or knowledge needed.

Provide the deviating CPU power up/down sequence for the die variant.
The new IP block uses per-core instead of per-cluster registers, but
follows the same pattern otherwise.

Since the CPU ops code is shared among all Allwinner SoCs, we need to
dummy-define the new register names for the older SoCs. The actual new
code is guarded by a predicate function, that is hard coded to return
true on the other SoCs. Since this is a static inline function in a
header file, the compiler will optimise away the unneeded branch there,
so the generated code for the other SoCs stays the same.

Change-Id: Ib5ade99d34b4ccb161ccde0e34f280ca6bd16ecd
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(allwinner): add function to detect H616 die variant

Allwinner provides a number of SoCs that use the same die as the H616.
Some of those chips apparently use a slight variation of that die, tha

feat(allwinner): add function to detect H616 die variant

Allwinner provides a number of SoCs that use the same die as the H616.
Some of those chips apparently use a slight variation of that die, that
differs in the way the CPU cores' power and reset controls are handled.
This die variation can be detected by reading the SRAM version register.

Provide a predicate function that returns false if that die variant is
used. Since the CPU power control code is shared for all supported SoCs,
we provide an instance of this function for each SoC, as a static
inline, and return true on all other SoCs. This allows to always use
this function, and still let the compiler optimise away the unneeded
branch for those older SoCs.

This function is unused for now, but is needed in the next patch.

Change-Id: I49e014b895b7e2f55b4e7dc2b3d8aa31cee711b5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(allwinner): add extra CPU control registers

The die used in several variants of the Allwinner H616 SoC (H313, T507)
seems to produced in at least two revisions. The newer one differs from
the o

feat(allwinner): add extra CPU control registers

The die used in several variants of the Allwinner H616 SoC (H313, T507)
seems to produced in at least two revisions. The newer one differs from
the original by using a different CPU control register IP block.

Add those newly used register offsets to the respective header file. The
MMIO block itself is actually present in both variants, though the
registers are different. The new registers tend to use one register per
core, in contrast to one register per cluster in the older revisions.

Change-Id: Ifbda1bdc67a6a16fbb901dbc83996e4a148b7602
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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