Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net):

Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net): move macros to common header
feat(xilinx): add support to get chipid

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fix(zynqmp): make zynqmp_devices structure smaller

Pack the structure and make id/ver smaller and sorted.
The change saves 400bytes in RODATA section.

Change-Id: I8bcbe8fd589ba193551a0dd2cd19572516

fix(zynqmp): make zynqmp_devices structure smaller

Pack the structure and make id/ver smaller and sorted.
The change saves 400bytes in RODATA section.

Change-Id: I8bcbe8fd589ba193551a0dd2cd19572516252e73
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "fix(brcm): fix misspelled header inclusion guard" into integration

Merge changes from topic "xilinx-ipi" into integration

* changes:
feat(xilinx): fix IPI calculation for Versal/NET
feat(xilinx): setup local/remote id in header
feat(xilinx): clean macro names

Merge changes from topic "xilinx-ipi" into integration

* changes:
feat(xilinx): fix IPI calculation for Versal/NET
feat(xilinx): setup local/remote id in header
feat(xilinx): clean macro names
fix(zynqmp): do not export apu_ipi
fix(zynqmp): remove unused headers
feat(xilinx): move IPI related macros to plat_ipi.h

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Merge "feat(versal-net): add the IPI CRC checksum macro support" into integration

feat(versal-net): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to ob

feat(versal-net): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.

Change-Id: I6648051c7f5fa27d2f02080209da36ee8d5a9d95
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(versal): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the

feat(versal): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.

Change-Id: I1466a9ad1bc8dde1cda516ddd3edbaa6a5941237
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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refactor(versal-net): move macros to common header

Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.

Change-Id: I355b024f5e8

refactor(versal-net): move macros to common header

Move the macros to common header from platform specific folder, so that
the same macros can be re-used in other platforms.

Change-Id: I355b024f5e870c6fc104598bc571dbaa29503ae2
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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feat(xilinx): add support to get chipid

Add support for PM API SYS to get the chip ID from the target.
The API calls the IPI command to read the Chip idcode and revision.

Change-Id: Id4d7d812cbf77c

feat(xilinx): add support to get chipid

Add support for PM API SYS to get the chip ID from the target.
The API calls the IPI command to read the Chip idcode and revision.

Change-Id: Id4d7d812cbf77c5e2fc7785b8afb379214f8dd19
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "fix(versal-net): fix BLXX memory limits for user defined values" into integration

Merge changes Ica1f9786,Ic96e3680 into integration

* changes:
fix(versal): fix BLXX memory limits for user defined values
fix(zynqmp): fix BLXX memory limits for user defined values

fix(versal-net): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker
fi

fix(versal-net): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker
file aligns section on a page boundary. So having the -1 in
the size calculations leads to an error message looking like this:

bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte

While at it fix all other occurences of predefined values that were
calculated with -1.

Fixes: 1d333e69091f ("feat(versal-net): add support for Xilinx
Versal NET platform")
Change-Id: I4455f63ee3ad52369f517a7d8d3627faf0b28c0f
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(versal): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
a

fix(versal): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:

bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte

While at it fix all other occurences of predefined values that were
calculated with -1

Fixes: commit f91c3cb1df7d4 ("arm64: versal: Add support for new Xilinx Versal ACAPs")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ica1f97867b701e7fcd60ea8ea07d2ae96c485443

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fix(zynqmp): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
a

fix(zynqmp): fix BLXX memory limits for user defined values

When compiling with user defined areas of memory the platform code
calculates the size with (base + size - 1). However, the linker file
aligns section on a page boundary. So having the -1 in the size
calculations leads to an error message looking like this:

bl31.elf section `coherent_ram' will not fit in region `RAM'
aarch64-buildroot-linux-uclibc-ld: region `RAM' overflowed by 1 byte

Commit 9b4ed0af02a8 ("feat(plat/zynqmp): fix section `coherent_ram' will not fit in region `RAM'")
applied a similar fix, but only in the predefined for BL31LIMIT/BASE.

While at it fix all other occurences of predefined values that were
calculated with -1

Fixes: 01555332faa48 ("zynqmp: Revise memory configuration options")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Change-Id: Ic96e36808d01f6bb92e6839cec92fc52320dd3f3

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Merge "fix(intel): update checking for memcpy and memset" into integration

Merge changes I38545567,I2f52d3ea into integration

* changes:
feat(intel): restructure sys mgr for S10/N5X
feat(intel): restructure sys mgr for Agilex

Merge "fix(ti): remove check for zero value in BL31 boot args" into integration

Merge "feat(intel): setup SEU ERR read interface for FP8" into integration

feat(intel): restructure sys mgr for S10/N5X

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for

feat(intel): restructure sys mgr for S10/N5X

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I385455671413e154d04a879d33fdd774fcfefbd6

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feat(intel): restructure sys mgr for Agilex

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for t

feat(intel): restructure sys mgr for Agilex

This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb

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fix(intel): update checking for memcpy and memset

Add checking on the size of source data does not exceed source size
when using memcpy and memset.

Add checking on the size of source data in FPGA C

fix(intel): update checking for memcpy and memset

Add checking on the size of source data does not exceed source size
when using memcpy and memset.

Add checking on the size of source data in FPGA Crypto Service does
not exceed the maximum of expected data size and does not meet the
minimum of expected data size.

Signed-off-by: Phui Kei Wong <phui.kei.wong@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idb18f05c18d9142fbe703c3f4075341d179d8bad

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fix(zynqmp): handling of type el3 interrrupts

The array type_el3_interrupt_table is defined for MAX_INTR_EL3(128)
elements and only two interrupts - ARM_IRQ_SEC_SGI_7(15), IRQ_TTC3_1(77)
are being h

fix(zynqmp): handling of type el3 interrrupts

The array type_el3_interrupt_table is defined for MAX_INTR_EL3(128)
elements and only two interrupts - ARM_IRQ_SEC_SGI_7(15), IRQ_TTC3_1(77)
are being handled. Current implementation is consuming 1024 bytes which
can be optimized for the number of interrupts to be handled.
The current array is replaced with the array of struct
zynmp_intr_info_type_el3_t (id and handler as member) and with
maximum number of interrupts to be handled as the size of array
(MAX_INTR_EL3 = 2). User is expected to adjust MAX_INTR_EL3 based on
how many interrupts are handled in TF-A.
With the updated implementation, a reduction of 960 bytes is observed.
Versal and Versal NET are using similar implementation introduced by
commit e497421d7f1e ("feat(versal): add infrastructure to handle
multiple interrupts") and commit 0654ab7f7544 ("feat(versal-net): add
support for platform management").

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I07aa388d38ac3ff3c0d25decbe0719087b27ee18

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feat(intel): setup SEU ERR read interface for FP8

Enable SEU ERR read interfaces for non-secure world to read out SEU status
for DDR.
SEU ERR SMC opcode updated to 0xC2000099

Signed-off-by: Jit Loo

feat(intel): setup SEU ERR read interface for FP8

Enable SEU ERR read interfaces for non-secure world to read out SEU status
for DDR.
SEU ERR SMC opcode updated to 0xC2000099

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I0618dfcdc86a7c1e0c8047b7214d369866dd2281

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fix(morello): remove platform specific pwr_domain_suspend wrapper

Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platf

fix(morello): remove platform specific pwr_domain_suspend wrapper

Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platform specific
psci pwr_domain_suspend handler.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I0a307cc140447e91fd0808fcfb309593f24c14ca

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fix(n1sdp): remove platform specific pwr_domain_suspend wrapper

Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platfor

fix(n1sdp): remove platform specific pwr_domain_suspend wrapper

Turning redistributor off during suspend disables any wakeup interrupts
resulting in cpu getting stuck. This patch removes the platform specific
psci pwr_domain_suspend handler.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ic2ad5a561be29eee9229a5cc11aa3c9320a51cb7

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