Merge changes from topic "st_fixes" into integration

* changes:
fix(st): enable RTC clock before accessing nv counter
fix(st-crypto): use GENMASK_32 to define PKA registers masks
fix(st): upda

Merge changes from topic "st_fixes" into integration

* changes:
fix(st): enable RTC clock before accessing nv counter
fix(st-crypto): use GENMASK_32 to define PKA registers masks
fix(st): update comment on encryption key
fix(st): allow crypto lib compilation in aarch64
fix(st-uart): allow 64 bit compilation
fix(st): reduce MMC block_buffer
fix(stm32mp13-fdts): cosmetic fixes in PLL nodes
fix(st): update dt_get_ddr_size() type
fix(nand): reset the SLC NAND
fix(st-crypto): do not read RNG data if it's not ready

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Merge "feat(mt8188): add DSB before udelay" into integration

Merge "feat(rmmd): enable SME for RMM" into integration

Merge changes from topic "xilinx-console-sync" into integration

* changes:
fix(xilinx): remove console error message
feat(xilinx): sync macro names
feat(xilinx): remove crash console unused ma

Merge changes from topic "xilinx-console-sync" into integration

* changes:
fix(xilinx): remove console error message
feat(xilinx): sync macro names
feat(xilinx): remove crash console unused macros

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feat(mt8188): add DSB before udelay

To ensure that all explicit memory accesses are complete before udelay,
insert dsb before udelay.

Change-Id: If119e920e29539ae8b68d3c44c8f77b5bf424a1a
Signed-off

feat(mt8188): add DSB before udelay

To ensure that all explicit memory accesses are complete before udelay,
insert dsb before udelay.

Change-Id: If119e920e29539ae8b68d3c44c8f77b5bf424a1a
Signed-off-by: Karl Li <karl.li@mediatek.com>

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feat(rmmd): enable SME for RMM

This patch enables Scalable Matrix Extension (SME) for RMM. RMM will
save/restore required registers that are shared with SVE/FPU register
state so that Realm can use

feat(rmmd): enable SME for RMM

This patch enables Scalable Matrix Extension (SME) for RMM. RMM will
save/restore required registers that are shared with SVE/FPU register
state so that Realm can use FPU or SVE.

The Relevant RMM support can be found here :
https://github.com/TF-RMM/tf-rmm/commit/0ccd7ae58b00

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I3bbdb840e7736dec00b71c85fcec3d5719413ffd

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Merge changes from topic "rm/handoff" into integration

* changes:
feat(qemu): implement firmware handoff on qemu
feat(handoff): introduce firmware handoff library

fix(xilinx): remove console error message

If console is not found there is no way where to print information about
it. Currently only cdns/dcc/pl011 uarts are supported that's why remove
the message

fix(xilinx): remove console error message

If console is not found there is no way where to print information about
it. Currently only cdns/dcc/pl011 uarts are supported that's why remove
the message which none can see anyway.
But keep "else" part with comment to avoid misra c rule 15.7 violation
which is also missing in Versal NET implementation.

Change-Id: I78e3baffd2288d2a4673099bf193f22029912840
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "refactor(ast2700): adopt RESET_TO_BL31 boot flow" into integration

Merge changes from topic "mp/fix_interrupt_type" into integration

* changes:
refactor(el3-runtime): plat_ic_has_interrupt_type returns bool
fix(el3-runtime): leverage generic interrupt controlle

Merge changes from topic "mp/fix_interrupt_type" into integration

* changes:
refactor(el3-runtime): plat_ic_has_interrupt_type returns bool
fix(el3-runtime): leverage generic interrupt controller helpers
fix(gicv3): map generic interrupt type to GICv3 group
chore(gicv2): use interrupt group instead of type

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refactor(ast2700): adopt RESET_TO_BL31 boot flow

Revise the AST2700 boot flow to the RESET_TO_BL31 scheme.
The execution of BL1/2 can be saved from ARM CA35 while most
low level platform initializat

refactor(ast2700): adopt RESET_TO_BL31 boot flow

Revise the AST2700 boot flow to the RESET_TO_BL31 scheme.
The execution of BL1/2 can be saved from ARM CA35 while most
low level platform initialization are moved to a preceding MCU.

This patch updates the build configuration and also adds
the SMP mailbox setup code to hold secondary cores until
they are being waken up.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I7e0aa6416b92b97036153db1d9a26baaa41b7b18

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feat(qemu): implement firmware handoff on qemu

Implement firmware handoff from BL2 to BL33 on qemu platform
compliant to Firmware handoff specification v0.9.

Change-Id: Id8d5206a71ef6ec97cf3c97995d

feat(qemu): implement firmware handoff on qemu

Implement firmware handoff from BL2 to BL33 on qemu platform
compliant to Firmware handoff specification v0.9.

Change-Id: Id8d5206a71ef6ec97cf3c97995de328ebf0600cc
Signed-off-by: Raymond Mao <raymond.mao@linaro.org>

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fix(st): enable RTC clock before accessing nv counter

The plat_get_nv_ctr() retrieves the non-volatile counter value from
TAMP_COUNTR register in RTCTAMP peripheral. The clock needs to be
enabled be

fix(st): enable RTC clock before accessing nv counter

The plat_get_nv_ctr() retrieves the non-volatile counter value from
TAMP_COUNTR register in RTCTAMP peripheral. The clock needs to be
enabled before accessing it.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I2e9fc2c7ac516d6f8624cc6c9d442ee85629bf9a

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fix(st): update comment on encryption key

On STM32MP2, the encryption key is 32 bytes, the key duplication
(done for 16 bytes OTP) is not done. Update the comment to precise that.

Change-Id: I6fc4d

fix(st): update comment on encryption key

On STM32MP2, the encryption key is 32 bytes, the key duplication
(done for 16 bytes OTP) is not done. Update the comment to precise that.

Change-Id: I6fc4d652fdd462808918e85f6e5bd0d68d10d436
Yann Gautier <yann.gautier@foss.st.com>

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Merge "fix(spmd): coverity scan issues" into integration

fix(st): allow crypto lib compilation in aarch64

Cast len with size_t, as it is unsigned long on Aarch64, and no more
unsigned int. Changing functions prototypes will not help as
.verify_signature a

fix(st): allow crypto lib compilation in aarch64

Cast len with size_t, as it is unsigned long on Aarch64, and no more
unsigned int. Changing functions prototypes will not help as
.verify_signature awaits an unsigned int for its last parameter.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I9332fd46301a9653af917802788fd97fe7c8a162

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fix(st-uart): allow 64 bit compilation

Change a %x in %zx to print a size_t variable.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I27ac3739f4a2ec3b33c34d2257fa858cbd1aae6a

fix(st): reduce MMC block_buffer

This buffer used by io_block should be the size on one block (512 bytes)
not 512*4 due to the use of uint32_t. Change that to uint8_t. This
reduces the size of BSS b

fix(st): reduce MMC block_buffer

This buffer used by io_block should be the size on one block (512 bytes)
not 512*4 due to the use of uint32_t. Change that to uint8_t. This
reduces the size of BSS by 1.5KiB.

Change-Id: I8492f13f5386679b0c81efba66911422412782f9
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(st): update dt_get_ddr_size() type

Move to size_t to ensure a generic algorithm whatever the platform
architecture.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7879367

fix(st): update dt_get_ddr_size() type

Move to size_t to ensure a generic algorithm whatever the platform
architecture.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I7879367849ed86750dcff2b6a15f4b998bf6da18
Signed-off-by: Sebastien PASDELOUP <sebastien.pasdeloup-ext@st.com>

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feat(xilinx): sync macro names

There is no reason to have platform specific macros where generic
macros can be used. This is pretty much preparation step for moving
console code to single location w

feat(xilinx): sync macro names

There is no reason to have platform specific macros where generic
macros can be used. This is pretty much preparation step for moving
console code to single location where multiple combinations can be
easier to handle.

Change-Id: I4d85ddef29f5870a9ea9590d4d1564469c6eb87e
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(xilinx): remove crash console unused macros

Macros are not used that's why remove them.

Change-Id: I4519ea0b9e30b757ab8a6ee3bb56af45dddc0d96
Signed-off-by: Michal Simek <michal.simek@amd.com>

Merge changes from topic "xilinx-crash" into integration

* changes:
feat(xilinx): used console also as crash console
feat(versal-net): remove empty crash console setup

feat(mt8188): update return value in mtk_emi_mpu_sip_handler

Remove the use of SMC_RET2 in the mtk_emi_mpu_sip_handler function. The
current smc driver in the atf driver has switched to using SMC_RE

feat(mt8188): update return value in mtk_emi_mpu_sip_handler

Remove the use of SMC_RET2 in the mtk_emi_mpu_sip_handler function. The
current smc driver in the atf driver has switched to using SMC_RET4 for
smc call clients. This change aligns the return value handling with the
updated driver behavior that ensures consistency and avoids potential
issues with the old return value.

Change-Id: I87f25b438d2119837c45bed80a8224fcfd141fb6
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>

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Merge "fix(corstone-1000): add cpu_helpers.S to platform.mk" into integration

refactor(el3-runtime): plat_ic_has_interrupt_type returns bool

Rather than returning 0 or 1, the above function returns bool false
or true. No functional change.

Change-Id: Iea904ffc368568208fa8203

refactor(el3-runtime): plat_ic_has_interrupt_type returns bool

Rather than returning 0 or 1, the above function returns bool false
or true. No functional change.

Change-Id: Iea904ffc368568208fa8203e0d2e0cdaa500b1e0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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