Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): suppo

Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): support BL32 (OP-TEE)

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Merge "fix(arm): derive RMM bank size from payload" into integration

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa)

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa): rename component_id to lfa_component_id

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fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.

Ref- https://developer.arm.com/documentation/102898/0108/

Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpus): add support for venom cpu

Add basic CPU library code to support Venom CPU

Change-Id: I84d4cb77b175812811a17e55b4b290585e05d216
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(rdaspen): support BL32 (OP-TEE)

Configure SPMC constants and Secure memory partition to boot BL32
image.

This also fixes the build to automatically accommodate BL33 if
BL32 base is not specif

feat(rdaspen): support BL32 (OP-TEE)

Configure SPMC constants and Secure memory partition to boot BL32
image.

This also fixes the build to automatically accommodate BL33 if
BL32 base is not specified, and removes a redundant entry for BL31
in platform definitions for mmap entries aswell.

Change-Id: I6a3ec97c8f41d6bddc4f20b6edc088a46e2caa75
Signed-off-by: Archish Venkatesh <Archish.Venkatesh@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge "feat(cpus): add support for Dionysus cpu library" into integration

Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platfor

Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platform hook for shared NV ctr

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chore(libfdt): update libfdt to v1.7.2

Where previously we cherry-picked individual sources from the libfdt
project tree, this change instead integrates the entire project tree
into the TF-A reposit

chore(libfdt): update libfdt to v1.7.2

Where previously we cherry-picked individual sources from the libfdt
project tree, this change instead integrates the entire project tree
into the TF-A repository. Doing so reduces the manual overhead of
updating libfdt in the future, as we avoid the need to analyse
individual source-level dependencies.

libfdt, conveniently, also provides a Makefile designed to ease its
integration into foreign build systems (like TF-A's), which we also make
use of in this change.

Source: https://git.kernel.org/pub/scm/utils/dtc/dtc.git/tree/?h=v1.7.2
Change-Id: I8babcfd27019fdd6d255d550491e1bb733745f27
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(kodiak): add support for RB3Gen2 platform

RB3Gen2 is an IoT platform based on Kodiak SoC. Details about this
platform can be found here [1]. The boot flow with TF-A/OP-TEE is:

PBL (ROM) -> X

feat(kodiak): add support for RB3Gen2 platform

RB3Gen2 is an IoT platform based on Kodiak SoC. Details about this
platform can be found here [1]. The boot flow with TF-A/OP-TEE is:

PBL (ROM) -> XBL -> BL2 -> BL31 -> BL33 -> Normal world OS
|
--> BL32

Steps to build TF-A for RB3Gen2:

$ make -j`nproc` PLAT=rb3gen2 SPD=opteed QTISECLIB_PATH=<qtiseclib-path>
BL32=<path-to-optee-bin> BL33=<path-to-os-bootloader-bin> fip all

$ ./tools/qti/generate_fip_elf.sh build/rb3gen2/release/fip.bin 0x9fc00000

The resulting fip.elf should be flashed in uefi_a partition on UFS flash
storage.

Note here that the bl2.elf generated requires to be signed as TZ image
with QTI signing involved. There is an ongoing effort to enable OEM only
signing for future boards support.

[1] https://www.qualcomm.com/developer/hardware/rb3-gen-2-development-kit

Change-Id: Ic19f28a5f559a0da28337f2d8da0d0e289a94514
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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feat(qti): introduce basic XPU driver

Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.

Change-Id: I2b5ad50c

feat(qti): introduce basic XPU driver

Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.

Change-Id: I2b5ad50c57b0112302d3568e0e0bcf2116d3e259
Co-developed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): introduce SoC codename as Kodiak

Qualcomm has recently started using SoC codenames for upstream support
with Linux kernel being the first adoptor. Using SoC codenames for
upstream pro

refactor(qti): introduce SoC codename as Kodiak

Qualcomm has recently started using SoC codenames for upstream support
with Linux kernel being the first adoptor. Using SoC codenames for
upstream projects removes the need to follow different product names
like for kodiak which is also known as sc7280, qcm6490 etc.

Let's follow this practice of using SoC codenames for TF-A project too
beginning with Kodiak. While doing that let's refactor SoC and board
specific files where the existing support for sc7280 has been renamed to
sc7280_chrome to reflect it's usage.

Change-Id: I236fadf8ae9550f94deb05ebfed17e2ddbd69509
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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feat(qti): add TF-A BL2 common platform framework

Currently QTI pltforms only supports coreboot as the second stage
bootloader. Lets enable support for TF-A BL2 as the common reference
second stage

feat(qti): add TF-A BL2 common platform framework

Currently QTI pltforms only supports coreboot as the second stage
bootloader. Lets enable support for TF-A BL2 as the common reference
second stage bootloader which is able to support a variety of normal
world OS bootloaders (BL33) like edk2, U-Boot, coreboot-depthcharge etc.

The common reference boot flow should look like following on QTI
platforms:

PBL (ROM) -> XBL -> BL2 -> BL31 -> BL33 -> Normal world OS
|
--> BL32

As of now XBL is performing DRAM initialization and loads two set of
images for BL2 and FIP into DRAM from flash after performing secure boot
checks if enabled. Then BL2 does the FIP parsing from DRAM and loads
payloads at appropriate addresses as per the FIP configuration.

Note here that BL2 image is loaded from TZ partition on UFS flash which
by default requires QTI secure boot checks.

Change-Id: Ice73905bff39291fa417389cb84dabe455c3f0ba
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): refactor RNG as a proper driver

Refactor QTI RNG as a proper driver rather than being present in
platform code aligning with common practice followed by other platforms.

Change-Id: I

refactor(qti): refactor RNG as a proper driver

Refactor QTI RNG as a proper driver rather than being present in
platform code aligning with common practice followed by other platforms.

Change-Id: I4c1f23b7ea2f17fdb71792319b4c403db542b757
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC

Follow common practice to enable config option PLAT_XLAT_TABLES_DYNAMIC
via platform.mk instead of platform_def.h.

Change-Id: I18944d5b5e97d784195c6df3

fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC

Follow common practice to enable config option PLAT_XLAT_TABLES_DYNAMIC
via platform.mk instead of platform_def.h.

Change-Id: I18944d5b5e97d784195c6df374892029e24f3d0b
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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feat(qti): add BL32 support

Add support for loading a BL32 image like OP-TEE. In this case we stop
routing secure EL3 interrupts to EL3 and instead allow S-EL1 to handle
them.

Change-Id: I8ba25f83c

feat(qti): add BL32 support

Add support for loading a BL32 image like OP-TEE. In this case we stop
routing secure EL3 interrupts to EL3 and instead allow S-EL1 to handle
them.

Change-Id: I8ba25f83cfc8749974fb5760392a8c64b2cec18b
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): make UART config independent

Make UART configuration independent of coreboot since there are
alternative bootloaders like TF-A BL2 which can be supported. Also,
configure UART scope t

refactor(qti): make UART config independent

Make UART configuration independent of coreboot since there are
alternative bootloaders like TF-A BL2 which can be supported. Also,
configure UART scope to enable runtime logging as well.

Change-Id: I1956535c769c2c3141854d062dc02c289b86b48d
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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refactor(qti): make CNTFRQ config independent

Make system counter frequency configuration independent of prior stage
boot-loader like coreboot to enable an alternative boot-loaders such as
TF-A BL2.

refactor(qti): make CNTFRQ config independent

Make system counter frequency configuration independent of prior stage
boot-loader like coreboot to enable an alternative boot-loaders such as
TF-A BL2.

Change-Id: Id22803557466643f6455a243929626f71a4714fc
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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fix(qti): fix build without coreboot

Skip some memory checks that rely on coreboot data.

Change-Id: I3c00aace547385af6b49632e3acfd9a977306a83
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.or

fix(qti): fix build without coreboot

Skip some memory checks that rely on coreboot data.

Change-Id: I3c00aace547385af6b49632e3acfd9a977306a83
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>

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feat(rdaspen): add support for configurable platform's CPU topology

- Add support for passing build time platform's CPU topology, which
defines the number of clusters and CPUs in the platform.
- A

feat(rdaspen): add support for configurable platform's CPU topology

- Add support for passing build time platform's CPU topology, which
defines the number of clusters and CPUs in the platform.
- Adjust the platform's power domain topology based on the passed
build time topology. If no build time topology was provided,
default topology will be used.

Change-Id: Ic80b308ab6d4c98139723021566d54be02b7d125
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>

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feat(rdaspen): scmi gracefully shutdown system

In RD-Aspen, RSE shall be responsible for system shutdown. When TF-A
send a graceful SCMI system power set command to SCP, SCP will not
execute the shu

feat(rdaspen): scmi gracefully shutdown system

In RD-Aspen, RSE shall be responsible for system shutdown. When TF-A
send a graceful SCMI system power set command to SCP, SCP will not
execute the shutdown but notify RSE runtime.

RD-Aspen enable the graceful flag of css_scp_system_off in
platform.mk.

Change-Id: I80967e1d2e85193dd98f626e4c729ac722251a53
Signed-off-by: Jun Wu <jun.wu@arm.com>

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fix(rdaspen): enable CPU feature runtime checking

Enable runtime feature detection for FEAT_AMU, FEAT_ECV, FEAT_FGT,
and FEAT_MTE2

These features were previously unconditionally enabled (=1) in the

fix(rdaspen): enable CPU feature runtime checking

Enable runtime feature detection for FEAT_AMU, FEAT_ECV, FEAT_FGT,
and FEAT_MTE2

These features were previously unconditionally enabled (=1) in the build
configuration, causing TF-A to initialize their contexts regardless of
actual CPU support in emulation implementations.

Set them to "2" to enable runtime feature detection instead.

With this change, TF-A checks the ID registers before accessing related
system registers or programming SCR_EL3 bits, avoiding register accesses
on CPUs that lack these features. This primarily addresses issues seen
in emulation environments with incomplete feature support.

Change-Id: I7f333245c60685544d925c24556358724a776082
Signed-off-by: Peter Hoyes <peter.hoyes@arm.com>

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Merge "feat(arm): load config after GPT FIP offset" into integration

feat(fwu): add platform hook for shared NV ctr

The NV ctr should not update when it is shared among
Bl1 and BL2. This is platform specific, therefore add
a platform hook to query the platform for th

feat(fwu): add platform hook for shared NV ctr

The NV ctr should not update when it is shared among
Bl1 and BL2. This is platform specific, therefore add
a platform hook to query the platform for this infor-
mation.

Change-Id: Ib180c8e6a183f7aaa7586e3f008273860d55b414
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "fix(tc): force specifying TARGET_PLATFORM" into integration