feat(rcar): deduplicate PWRC timer

The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mai

feat(rcar): deduplicate PWRC timer

The PWRC timer code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: Id50a730ea58faedaa24380fd3171be171ecd7269

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feat(rcar): deduplicate PWRC SRAM trampoline

The PWRC SRAM trampoline code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <mar

feat(rcar): deduplicate PWRC SRAM trampoline

The PWRC SRAM trampoline code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I24209ac0277fa12898bbeea69d93a8f057e76ed4

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feat(rcar): deduplicate stack protector

The stack protector code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+r

feat(rcar): deduplicate stack protector

The stack protector code is functionally identical between
Renesas R-Car Gen3 and R-Car Gen4, deduplicate the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I1caf6cc6a9ace678b50013eee1a5506fba9acccc

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chore(xilinx): add deprecation warning to pm_feature_check

Add deprecation warning to pm_feature_check() function to inform
users that this API will be removed in the 2027.1 release and
they should

chore(xilinx): add deprecation warning to pm_feature_check

Add deprecation warning to pm_feature_check() function to inform
users that this API will be removed in the 2027.1 release and
they should migrate to tfa_api_feature_check() for TF-A specific
feature checks.

This warning helps customers prepare for the upcoming API removal
and encourages migration to the correct function.

Change-Id: Icab5eb6f1a552553b1cc1215aa683430733667bd
Signed-off-by: Devanshi Chauhan <devanshi.chauhan@amd.com>

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refactor(xilinx): rename eemi_feature_check to tfa_api_feature_check

Rename eemi_feature_check() to tfa_api_feature_check() for better
clarity. The new name clearly indicates its purpose of handling

refactor(xilinx): rename eemi_feature_check to tfa_api_feature_check

Rename eemi_feature_check() to tfa_api_feature_check() for better
clarity. The new name clearly indicates its purpose of handling TF-A
specific feature checks and improves code maintainability.

Change-Id: Ia74b12933427ccadbc8ede5ddc2a7a4822766264
Signed-off-by: Devanshi Chauhan <devanshi.chauhan@amd.com>

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fix(versal): modify IPI4 and IPI5 trigger bit definitions

The IPI4 and IPI5 trigger bit definitions are incorrect according
to the register database specification. This discrepancy can
cause IPI com

fix(versal): modify IPI4 and IPI5 trigger bit definitions

The IPI4 and IPI5 trigger bit definitions are incorrect according
to the register database specification. This discrepancy can
cause IPI communication failures between processing units in
Versal SoCs. So, modified the trigger bits to align the software
definitions with the hardware register specification as documented
in the register database.

Change-Id: I1e32961124daf8e5635906fb615e98a650130f27
Signed-off-by: Devanshi Chauhan <devanshi.chauhan@amd.com>

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fix(build): correctly detect that an option is missing with ld_option

We support building directly with ld and indirectly with gcc. The
`ld_option` macro is oblivious to this and does a check for bo

fix(build): correctly detect that an option is missing with ld_option

We support building directly with ld and indirectly with gcc. The
`ld_option` macro is oblivious to this and does a check for both styles
of invocation. However, the gcc one is incorrect - gcc returns `0` even
when it has printed an error saying that it doesn't recognise the
option. Add a discovery function for each linker we expect and
dynamically dispatch to the correct one.

While we're at it, also add a little bit of code to return the -Wl
prefix for gcc and not for ld.

All of the above is also true for clang and lld, although they don't
suffer from the problem that gcc does.

Change-Id: I4f7bdf40c01f4c5df9c177f5048f5e349bc2b9c9
Co-authored-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes I44f90daa,I0fed6ef4,I018869d3,I9089b3ad,Ibf5b3a80 into integration

* changes:
refactor(fvp): always build RAS files
fix(fvp): give fvp_ras.c better dependencies
fix(cpufeat): add

Merge changes I44f90daa,I0fed6ef4,I018869d3,I9089b3ad,Ibf5b3a80 into integration

* changes:
refactor(fvp): always build RAS files
fix(fvp): give fvp_ras.c better dependencies
fix(cpufeat): add ras files to the build from a common location
fix(cm): do not restore spsr and elr twice on external aborts
fix(cm): do not save SCR_EL3 on external aborts

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feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those

feat(cpufeat): enable FEAT_AIE support

Implement support for FEAT_AIE, which introduces the AMAIR2_ELx and
MAIR2_ELx system registers, extending the memory attributes described
by {A}MAIR_ELx.
Those system registers are trapped by the SCR_EL3.AIEn bit, so set the
bit for the non-secure world context to allow OSes to use the feature.

This is controlled by the ENABLE_FEAT_AIE build flag, which follows the
usual semantics of 2 meaning the feature being runtime detected.
Let the default for this flag be 0, but set it to 2 for the FVP.

Change-Id: Iba2011719013a89f9cb3a4317bde18254f45cd25
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE acr

feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE across all AMD-Xilinx platforms.

Change-Id: I95465e29ac8a9370da135c2113203c3206ecfec0
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was

fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was passed to the firmware which is incorrect. Pass NON_SECURE
flag from the platform specific file to the firmware in order to
align with the PSCI specification.

Change-Id: Iabe2cb45467cf63fe36626d323513ff05548eb3b
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359

fix(intel): update nand driver to enable Linux OS boot

Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.

Change-Id: If592680ef359378574b913b11d466c89389a2606
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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fix(rcar3): clear TCR_EL1 at the BL2 entry point

According to ARM DDI0601 2025-06 [1] TCR_EL1, Translation Control
Register (EL1), all fields of TCR_EL1 do, on a Warm reset, (this
field) resets to a

fix(rcar3): clear TCR_EL1 at the BL2 entry point

According to ARM DDI0601 2025-06 [1] TCR_EL1, Translation Control
Register (EL1), all fields of TCR_EL1 do, on a Warm reset, (this
field) resets to an architecturally UNKNOWN value.

On some SoCs, after reset, this TCR_EL1 may not be 0, which in itself
is perfectly valid behavior. However, existing software may depend on
TCR_EL1 being 0, and the UNKNOWN value may confuse such software.

Reset TCR_EL1 to well defined value 0 at BL2 entrypoint to achieve
maximum compatibility.

[1] https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/TCR-EL1--Translation-Control-Register--EL1-

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # update commit message
Change-Id: If3a1d40291b9b9768a8fc55e750bd742f3cc4ddc
---
Note: This is related to MR 25532 , but with reworked commit message
and broken out from the large work-in-progress series.

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refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

refactor(build): avoid implicit pattern rules

This change translates any implicit pattern rules into the equivalent
static pattern rules, i.e. rules like:

%.o: %.s
...

... become:

$(OBJS): %.o: %.s
...

These behave similarly, but have some subtle differences. The former
defines a rule "for any target matching %.o where there is not a more
specific rule", whereas the latter defines a rule "for these targets,
which match %.o".

Where possible it is better to use a static pattern rule as it reduces
the rule space that Make needs to search.

Change-Id: Ifba4f44bcecf4e74980c31347e192cdf1e42003e
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "fix(rcar3): add missing image_base/size assignment to BL33 image loading path" into integration

Merge "fix(intel): undo setting USB 3.1 reset pulse bit in BL2" into integration

Merge "fix(intel): update the AES GCM/GCM_GHASH modes return data size" into integration

Merge "fix(intel): configure SCR1 for 32/16 non-secure SMRs and context banks" into integration

Merge "fix(arm): don't override the gic redistributor frames" into integration

Merge "fix: remove unused cpu_data related macros" into integration

Merge "fix(fvp): do not unregister the console on system suspend" into integration

fix(fvp): do not unregister the console on system suspend

On PSCI SYSTEM_SUSPEND, Arm platforms will call
arm_system_pwr_domain_save() which will call arm_console_runtime_end().
Usually (eg CSS), th

fix(fvp): do not unregister the console on system suspend

On PSCI SYSTEM_SUSPEND, Arm platforms will call
arm_system_pwr_domain_save() which will call arm_console_runtime_end().
Usually (eg CSS), that's just a flush, but on FVP that also unregisters
the console. On HW_ASSISTED_COHERENCY=0 builds, this has the potential
to break and prevent any EL3 output after a SYSTEM_SUSPEND.

This happens because the calls to
console_unregister()/console_register() will overwrite the value of the
console_list variable in drivers/console/multi_console.c. They are
only called on a system level suspend. The bug happens when the core
wakes up. The console will be registered again as part of the
pwr_domain_suspend_finish() call. However, this call happens before the
data caches have been enabled in psci_do_pwrup_cache_maintenance(). As a
result, the write to console_list will not be reflected in the L2 cache
and other cores will not be able to read the new value.

The fix is to not unregister the console like other Arm platforms -
we don't need to reinitialise the console so there's nothing to do.

A nice side effect is that arm_console_runtime_end() no longer needs to
be weak.

Change-Id: Ibbdd4b22bad0d8f1dbd63c60ee0294d889a349a4
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration

* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add

Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration

* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add DSU support
docs(rdaspen): introduce rdaspen docs
feat(rdaspen): enable tbb on rd-aspen platform
feat(gicv3): add GIC-720AE model id
feat(rdaspen): add BL31 for RD-Aspen platform
feat(rdaspen): introduce Arm RD-Aspen platform

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Merge "fix(gpt): fix fill_l1_cont_desc() function" into integration

Merge "feat(xilinx): deprecate PM_REQ_SUSPEND EEMI API" into integration