fix(versal2): remove SCMI drivers in NO PM configuration

Remove SCMI message driver and related sources when TFA_NO_PM=1,
as SCMI functionality is only relevant when power management is
enabled.

Wh

fix(versal2): remove SCMI drivers in NO PM configuration

Remove SCMI message driver and related sources when TFA_NO_PM=1,
as SCMI functionality is only relevant when power management is
enabled.

When TF-A is built without PM support (TFA_NO_PM=1), the platform
only needs basic PSCI support. The SCMI server implementation and
scmi-msg drivers are unnecessary in this configuration and should
be excluded from the build.

Changes:
- Remove SCMI-related source files from BL31_SOURCES in NO PM path
- Delete scmi.c implementation (clock, reset, power domain stubs)
- Keep only minimal plat_psci.c for basic PSCI functionality

This reduces binary size and removes unused code paths when SCMI
services are not required.

Change-Id: I33397b1fa32e309728042b1bdba07aa6ad02c844
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

feat(amd): custom package linker infra

Add linker script consolidation framework for custom packages
integrated with TF-A.

- Implement two-stage preprocessing for custom linker scripts
- Auto-disco

feat(amd): custom package linker infra

Add linker script consolidation framework for custom packages
integrated with TF-A.

- Implement two-stage preprocessing for custom linker scripts
- Auto-discover custom_pkg.ld.S files in package directories
- Create linker script template (plat.ld.S.tpl) for consolidation
- Support normalized absolute path resolution for multiple packages
- Generate final plat.ld.S by preprocessing template with custom scripts

The framework automatically discovers and preprocesses custom package
linker scripts, expanding package-specific macros before inclusion in
the final consolidated linker script. This enables multiple packages
to define custom memory regions and sections without conflicts.

Change-Id: Ie21e807f96507a655275443df5f33b18915965f8
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

chore(versal2): make TFA_NO_PM configurable with default value

Change TFA_NO_PM from a hardcoded assignment (TFA_NO_PM := 0) to
a conditional assignment using the ?= operator (TFA_NO_PM ?= 0).
Move

chore(versal2): make TFA_NO_PM configurable with default value

Change TFA_NO_PM from a hardcoded assignment (TFA_NO_PM := 0) to
a conditional assignment using the ?= operator (TFA_NO_PM ?= 0).
Move the definition after custom package integration to ensure
proper initialization order.

This allows users to override TFA_NO_PM at build time while
maintaining a sensible default value (disabled PM by default).
The reordering ensures TFA_NO_PM is defined after CUSTOM_PKG_PATH
processing, preventing unintended overwrites by build-time
customizations.

Change-Id: I864f3a53f7b0614bef9dbdab727ed1c82156363a
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

feat(amd): support multiple custom packages

Add support for including multiple custom packages to be built and
linked with TF-A for AMD platforms. This allows flexible integration
of multiple custom

feat(amd): support multiple custom packages

Add support for including multiple custom packages to be built and
linked with TF-A for AMD platforms. This allows flexible integration
of multiple custom service implementations.

- Introduce custom_pkg.mk for custom package integration
- Create custom_svc_stub.c with default stub implementations
- Refactor platform.mk to conditionally include custom packages
- Support multiple package paths via space/semicolon-separated
CUSTOM_PKG_PATH

The framework handles discovery and inclusion of custom_pkg.mk files
from each package directory, providing flexibility for platform-specific
customizations without modifying TF-A core code.

Change-Id: I254373f81744328a3e7d5fcf482d137c7108444f
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

show more ...

feat(k3low): re-configure firewalls for TI AM62L

In TI AM62L SoC, some of the firewalls are configured by ROM during
boot, or are at their default configurations. These firewalls are not
necessary a

feat(k3low): re-configure firewalls for TI AM62L

In TI AM62L SoC, some of the firewalls are configured by ROM during
boot, or are at their default configurations. These firewalls are not
necessary after the boot phase. For an HS-SE(SECURE ENFORCED) type
device, where the security goals are fully enforced, this causes
firewall exception when those regions are accessed from non-secure A53
core.

This commit adds changes to properly configure firewalls for AM62L SoC
initialization to remove the appropriate firewalls. A similar approach
is used for some other K3 TI SoCs, but in U-Boot. This code is based on
the U-Boot K3 firewall disabling code. Link:
https://github.com/u-boot/u-boot/blob/f9ffeec4bdcf1da655a0ffea482062adde78fee8/arch/arm/mach-k3/r5/common.c#L282

Change-Id: I6dd81d0544e181a58ce963ff9d724f465c764da0
Signed-off-by: T Pratham <t-pratham@ti.com>

show more ...

feat(s32g274ardb): add DDR init call

Add support for DDR initialization through
`ddr_init()` integration. This call enables
proper initialization of DDR memory during
`bl2_plat_handle_post_image_loa

feat(s32g274ardb): add DDR init call

Add support for DDR initialization through
`ddr_init()` integration. This call enables
proper initialization of DDR memory during
`bl2_plat_handle_post_image_load` stage.

Change-Id: Ib7da7d6af2e2b512746d12f05cb3dd7bf62667f0
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

feat(s32g274ardb): map regions used by DDR driver

Map DDR PHY and GPR regions to enable DDR
initialization. The DDR driver requires these
mappings to program the DDR controller and
system level conf

feat(s32g274ardb): map regions used by DDR driver

Map DDR PHY and GPR regions to enable DDR
initialization. The DDR driver requires these
mappings to program the DDR controller and
system level configuration registers.

Change-Id: I0d6ac5643abd2966215ad9a27cd7bd09c4ffe720
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

fix(versal2): update IRQ_MAX for SDIO interrupts

IRQ_MAX is defined as 200U but the irq_to_pm_node_idx()
function handles IRQ numbers up to 220 for SDIO devices
(IRQ 218 for SDIO_0 and IRQ 220 for S

fix(versal2): update IRQ_MAX for SDIO interrupts

IRQ_MAX is defined as 200U but the irq_to_pm_node_idx()
function handles IRQ numbers up to 220 for SDIO devices
(IRQ 218 for SDIO_0 and IRQ 220 for SDIO_1).

This mismatch causes a runtime assertion failure when SDIO
interrupts are processed, preventing proper SDIO device power
management.

Update IRQ_MAX to 220U to accommodate the highest IRQ number
actually handled by the platform.

Change-Id: Icc78e4325750c69d8b50423675f256314993ecec
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

show more ...

feat(rk3568): protect TF-As memory area with the DDR firewall

Similar to most (all?) other Rockchip SoCs, the RK3568 also has a DDR
firewall to restrict memory regions to secure usage.

The original

feat(rk3568): protect TF-As memory area with the DDR firewall

Similar to most (all?) other Rockchip SoCs, the RK3568 also has a DDR
firewall to restrict memory regions to secure usage.

The original submission didn't protect the TF-A's memory region, so
implement this now with knowledge gained from comments in the OPTEE
pull-request for the rk356x [0].

Contrary to other SoCs like RK3576 and RK3588, the RK3568 memory
regions are managed in blocks of 128KB, not blocks of 1MB size.
With the registers having 16bit for upper and lower block id, this then
can completely fill the 8GB max ram size the RK356x supports.

The whole behaviour was tested with a number of reads from main u-boot.
With the current config of protecting everything in the first MB of memory,
doing any reads before the 1MB border will trigger the expected
"Synchronous Abort" and restart.

So doing
=> md 0x100000 4
will succeed, but reading anything before this will trigger the Abort.

[0] https://github.com/OP-TEE/optee_os/pull/6954#issuecomment-3041255974

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Diederik de Haas <diederik@cknow-tech.com>
Change-Id: I6c75ab2813566e727e46cea86dd229625a64dd3f

show more ...

feat(rk3568): bring DDR firewall naming in line

The TRM declares that region as FIREWALL_DDR, so name the memory region
accordingly in TF-A and also remove the double FW_DDR + _REG addon from
the on

feat(rk3568): bring DDR firewall naming in line

The TRM declares that region as FIREWALL_DDR, so name the memory region
accordingly in TF-A and also remove the double FW_DDR + _REG addon from
the one known register.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ic098baa13b5c0b4cf339905030ee7d777bcbda34

show more ...

feat(rk3568): move existing secure init to separate files

Move the existing secure_timer_init() and sgrf_init() to a separate
file similar to the other Rockchip platforms.

This allows us to add add

feat(rk3568): move existing secure init to separate files

Move the existing secure_timer_init() and sgrf_init() to a separate
file similar to the other Rockchip platforms.

This allows us to add additional secure init later on.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I1151abed77d68b3730d505c547919e60415e3951

show more ...

fix(rockchip): fix comment and value about TZRAM_SIZE

TZRAM_SIZE is 0x100000 which is 1MB, not 512KB as the comment suggests.
Additionally using the existing SZ_1M constant is way nicer.

Signed-off

fix(rockchip): fix comment and value about TZRAM_SIZE

TZRAM_SIZE is 0x100000 which is 1MB, not 512KB as the comment suggests.
Additionally using the existing SZ_1M constant is way nicer.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I277347963b93f7ac69897cc1be252087521882e4

show more ...

feat(s32g274ardb): add DDR FW entry to storage

Add DDR firmware entry to storage `policies`
array.

Add DDR firmware image to `bl2_mem_params_descs`
for proper DDR firmware loading during early
boot

feat(s32g274ardb): add DDR FW entry to storage

Add DDR firmware entry to storage `policies`
array.

Add DDR firmware image to `bl2_mem_params_descs`
for proper DDR firmware loading during early
boot.

Change-Id: I41133fd9c8341d4be387c2de7b083739bede3605
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

Merge "feat(s32g274ardb): load BL31 and BL33 to DDR" into integration

Merge "fix(rcar5): enable SVE support for secure world" into integration

feat(s32g274ardb): load BL31 and BL33 to DDR

Update the platform memory layout to load BL31
and BL33 to DDR instead of SRAM, as it is now
initialized and available.

The `BL31_BASE` and `BL33_BASE`

feat(s32g274ardb): load BL31 and BL33 to DDR

Update the platform memory layout to load BL31
and BL33 to DDR instead of SRAM, as it is now
initialized and available.

The `BL31_BASE` and `BL33_BASE` are removed from
`platform_mem_init()` since these images are no
longer loaded into SRAM and should not be initialized
before DDR setup.

Change-Id: Ic12c86b9e66ba710cbd5a42a206f2cd736411956
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
Signed-off-by: Andra-Teodora Ilie <andra.ilie@nxp.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@nxp.com>

show more ...

Merge "fix(build): use assignment instead of memcpy to avoid a GCC 11 bug" into integration

Merge "refactor(platforms): remove A5DS platform (EOL)" into integration

fix(marvell): work around uutils coreutils truncate -s %SIZE bug

The boot-image.bin assembly uses "truncate -s %128K" to pad bl1.bin
to a 128 KiB boundary before appending the FIP. This ensures the

fix(marvell): work around uutils coreutils truncate -s %SIZE bug

The boot-image.bin assembly uses "truncate -s %128K" to pad bl1.bin
to a 128 KiB boundary before appending the FIP. This ensures the FIP
starts at offset 0x20000, which is where BL1 expects it at runtime
(PLAT_MARVELL_FIP_BASE = PLAT_MARVELL_ATF_LOAD_ADDR + 0x20000).

uutils coreutils (Rust rewrite of GNU coreutils), shipped as the
default coreutils on Ubuntu 25.04+, has a bug in its truncate
implementation of the "%" (round up to multiple) operator.

The RoundUp formula at line 71 of src/uu/truncate/src/truncate.rs
in uutils coreutils 0.5.0 is:

fsize + fsize % size

The correct formula (used by GNU coreutils and fixed on uutils main
branch) is:

checked_next_multiple_of(fsize, size)

which is equivalent to: fsize + (size - fsize % size) % size

Example with bl1.bin (24696 bytes) and "truncate -s %128K":

GNU coreutils: 24696 + (131072 - 24696 % 131072) % 131072
= 24696 + 106376 = 131072 (0x20000) -- correct

uutils 0.5.0: 24696 + 24696 % 131072
= 24696 + 24696 = 49392 (0xC0F0) -- wrong

As a result, the FIP is placed at offset 0xC0F0 instead of 0x20000
in boot-image.bin. BL1 then fails at runtime with:

WARNING: Firmware Image Package header check failed.
WARNING: Failed to obtain reference to image id=1 (-2)
ERROR: Failed to load BL2 firmware.

The workaround detects the bug at make parse time by creating a
1-byte test file and checking whether "truncate -s %128K" produces
131072 bytes. If not, it falls back to explicit numeric sizes.

Reference: uutils coreutils 0.5.0 buggy source:
https: //github.com/uutils/coreutils/blob/0.5.0/src/uu/truncate/src/truncate.rs#L71
Change-Id: I208a7ca7ca4c113817969935c26bd0c7f0207d7d
Signed-off-by: Vincent Jardin <vjardin@free.fr>

show more ...

fix(a8k): add XFI params for NBX SFI 10G

Add XFI static values for CP0 and CP1 Comphy4 lanes which connect to
the SFP+ cages on the NBX board. The tuning values for a80x0
configures the SerDes equal

fix(a8k): add XFI params for NBX SFI 10G

Add XFI static values for CP0 and CP1 Comphy4 lanes which connect to
the SFP+ cages on the NBX board. The tuning values for a80x0
configures the SerDes equalizer, TX amplitude, pre-emphasis and RX filter
coefficients for 10.3125 Gbps operation of both 10G ports of the CPU.

Change-Id: Ic4f0fb6331c504f98cb7e832848dd3481931dbb7
Signed-off-by: Vincent Jardin <vjardin@free.fr>

show more ...

fix(a8k): mv_ddr path may not be a git repo

When the mv-ddr-marvell folder is not a git tree the build fails
complaining that it "does not contain valid mv-ddr-marvell git
repository".

For instance

fix(a8k): mv_ddr path may not be a git repo

When the mv-ddr-marvell folder is not a git tree the build fails
complaining that it "does not contain valid mv-ddr-marvell git
repository".

For instance, it shall be removed when Building using Buildroot.

Change-Id: Ieaff6281785993873c7cb26ddc1d90d0896ad1b7
Signed-off-by: Vincent Jardin <vjardin@free.fr>

show more ...

feat(a8k): add a80x0_nbx Free Mobile board

Add TF-A platform support for the a80x0_nbx board (Free Mobile
Nodebox10G), a network appliance based on the Marvell Armada 8040
SoC with dual CP110 compan

feat(a8k): add a80x0_nbx Free Mobile board

Add TF-A platform support for the a80x0_nbx board (Free Mobile
Nodebox10G), a network appliance based on the Marvell Armada 8040
SoC with dual CP110 companion processors.

Hardware configuration:
- Quad-core ARM Cortex-A72 @ 1.3GHz
- DDR4 memory with ECC support (single channel, 32-bit)
- Dual CP110 companion processors (CP0 and CP1)
- SGMII 1G Ethernet on CP0 lane 5
- I2C buses for peripheral access (CP0: 100kHz, CP1: 400kHz)
- NS16550 UART console at 115200 baud
- eMMC boot via Xenon SDHCI controller

Key features implemented:

1. Ramoops buffer preservation across cold boot (ramoopsies driver)
On ECC-enabled DDR configurations, the memory controller must
scrub all memory during initialization to establish valid parity
bits. This would normally destroy the Linux kernel ramoops buffer
containing crash logs from the previous boot. The ramoopsies
driver intercepts the DDR scrubbing function using the GNU linker
--wrap feature, saving the 32KB ramoops buffer (at 0x3FFF8000) to
SRAM before scrubbing and restoring it afterward. The driver also
handles pending SError exceptions that occur when reading
uninitialized ECC memory by installing a minimal exception vector
that acknowledges and clears them.

2. UART-based skip image recovery mechanism
The platform uses the USER_DEFINED skip image detection callback
to implement software-based boot recovery without requiring a
dedicated GPIO button. Users can trigger recovery mode by holding
the 's' key during early boot, causing the bootloader to load
from the secondary/recovery image instead of the primary firmware.

3. SerDes/ComPhy configuration
PHY porting layer configured with default tuning values for
XFI (10G) and SATA interfaces, following the principle of minimal
bootloader configuration. Advanced SerDes tuning is deferred to
the Linux kernel where it can be more easily adjusted.

The implementation includes comprehensive documentation and a build
verification script to validate proper symbol exports, DDR driver
integration, and flash image format compliance.

Based on original work by Nicolas Schichan <nschichan@freebox.fr>
for the ramoops preservation mechanism and USER_DEFINED skip image
detection concept.

Change-Id: Iaacbb29631f27b47fbf5cc300d8c63aaf1e89e51
Signed-off-by: Vincent Jardin <vjardin@free.fr>

show more ...

Merge "fix(juno): debug build fail with MEASURED_BOOT and SPMC_AT_EL3" into integration

Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STE

Merge changes from topic "bk/new_feats" into integration

* changes:
feat(cpufeat): add support for FEAT_HACDBS
feat(cpufeat): add support for FEAT_HDBSS
feat(cpufeat): add support for FEAT_STEP2
feat(docs): update the feature guide to mention FEAT_IDTE3
fix(cpufeat): remove the feature list from arch_features.h
docs(cpufeat): add analysis of 2022 features
fix(cpus): use hint instruction instead of the psb mnemonic

show more ...

Merge changes from topic "upstream_add_ddr_fw" into integration

* changes:
feat(s32g274ardb): add support for DDR img in FIP
feat(s32g274ardb): add DDR FW binary check