Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc):

Merge changes from topic "us_pmu" into integration

* changes:
fix(tc): correct CPU PMU binding
feat(tc): add device tree binding for SPE
feat(tc): add PPI partitions in DT binding
feat(tc): change GIC DT property 'interrupt-cells' to 4
feat(tc): add NI-Tower PMU node for TC3
feat(tc): setup ni-tower non-secure access for TC3

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feat(tc): setup ni-tower non-secure access for TC3

NI-Tower's component's registers are need to be accessed from
kernel NI-PMU driver so enable NS access to it.

Change-Id: I83a8b3a1d2778baf767ff932

feat(tc): setup ni-tower non-secure access for TC3

NI-Tower's component's registers are need to be accessed from
kernel NI-PMU driver so enable NS access to it.

Change-Id: I83a8b3a1d2778baf767ff93263e246d127ef8114
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge changes from topic "corstone1000-bugfixes" into integration

* changes:
fix(corstone1000): update memory layout comments
fix(corstone1000): clean cache and disable interrupt before system r

Merge changes from topic "corstone1000-bugfixes" into integration

* changes:
fix(corstone1000): update memory layout comments
fix(corstone1000): clean cache and disable interrupt before system reset
fix(corstone1000): remove unused NS_SHARED_RAM region
fix(corstone1000): pass spsr value explicitly

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fix(corstone1000): update memory layout comments

The SRAM (CVM) memory layout was outdated in the platform_defs.h of
the Corstone-1000 platform. Updated it to list every bootloaders and
to be aligne

fix(corstone1000): update memory layout comments

The SRAM (CVM) memory layout was outdated in the platform_defs.h of
the Corstone-1000 platform. Updated it to list every bootloaders and
to be aligned with the implementation. Also added the starting (base)
addresses of each partition.

Change-Id: Ie8e8416ee2650ff25a8d4c61d8d9af789bc639c1
Signed-off-by: Bence Balogh <bence.balogh@arm.com>

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fix(corstone1000): clean cache and disable interrupt before system reset

Corstone1000 does not properly clean the cache and disable gic interrupts
before the reset. This causes a race condition espe

fix(corstone1000): clean cache and disable interrupt before system reset

Corstone1000 does not properly clean the cache and disable gic interrupts
before the reset. This causes a race condition especially in FVP after
reset. This adds proper sequence before resetting the platform.

Change-Id: I22791eec2ec0ca61d201d8a745972a351248aa3d
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>

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fix(arm): move HW_CONFIG relocation into BL31

Refactor DT relocation logic from BL2 to BL31 for non-secure DRAM.
Previously, BL2 was responsible for copying the DT into SRAM and DRAM,
resulting in d

fix(arm): move HW_CONFIG relocation into BL31

Refactor DT relocation logic from BL2 to BL31 for non-secure DRAM.
Previously, BL2 was responsible for copying the DT into SRAM and DRAM,
resulting in duplicate code in BL31 to cater for the `RESET_TO_BL31`
case. By moving the re-location logic to BL31, we simplify handling of
the non-secure DT and TL.

Change-Id: Id239f9410669afe4b223fa8d8bb093084a0e5e1b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(ast2700): fix mpll calculate statement

pll_reg.b.bypass equal to 1U, bypass the mpll calculating
pll_reg.b.bypass equal to 0U, need to calculate mpll

Change-Id: I6cace1509d9429a97c7c9481dc1e2e4

fix(ast2700): fix mpll calculate statement

pll_reg.b.bypass equal to 1U, bypass the mpll calculating
pll_reg.b.bypass equal to 0U, need to calculate mpll

Change-Id: I6cace1509d9429a97c7c9481dc1e2e4f95134d6c
Signed-off-by: Kevin Chen <kevin_chen@aspeedtech.com>

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Merge "fix(allwinner): dtb: check for correct error condition" into integration

fix(allwinner): dtb: check for correct error condition

In sunxi_soc_fdt_fixup(), we check for the value of "ret" again, after
calling fdt_node_offset_by_phandle(), even though the error value of
tha

fix(allwinner): dtb: check for correct error condition

In sunxi_soc_fdt_fixup(), we check for the value of "ret" again, after
calling fdt_node_offset_by_phandle(), even though the error value of
that lands in "node".

Check for "node" being non-negative instead, to properly detect any
errors here.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I57c1406388dbe11d343038da173019519e18af3e

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feat(xilinx): add feature check function for TF-A specific APIs

Currently, there is common feature check function for firmware APIs
and TF-A specific APIs. This should be separate from firmware APIs

feat(xilinx): add feature check function for TF-A specific APIs

Currently, there is common feature check function for firmware APIs
and TF-A specific APIs. This should be separate from firmware APIs.
So add new TF-A API for feature check of TF-A specific APIs.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I5585d17fb6aa1e98989d935117cca10bdb85133e

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feat(xilinx): update SiP SVC version number

SMC ID is fixed in new SiP SVC call format while it varies according
to PLM header in old Linux. So, enhance SIP_SVC_VERSION number to
support backward co

feat(xilinx): update SiP SVC version number

SMC ID is fixed in new SiP SVC call format while it varies according
to PLM header in old Linux. So, enhance SIP_SVC_VERSION number to
support backward compatibility and to use full request and response
buffer from bare-metal or Linux.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I6764cc92b33b7366640f553827e80c5e97985fcf

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feat(xilinx): update TF-A to passthrough all PLM commands

Currently, the IDs used in PLM CMD header are mixed with SMC IDs in
TF-A which is restricting the range of IDs that can be used by PLM.
Also

feat(xilinx): update TF-A to passthrough all PLM commands

Currently, the IDs used in PLM CMD header are mixed with SMC IDs in
TF-A which is restricting the range of IDs that can be used by PLM.
Also, the SMC call from firmware driver is passing all 7 32-bit
words in request but TF-A is not passing all of them to firmware and
TF-A passes only 4 32-bit words from firmware to Linux in response.

So, update TF-A to passthrough all PLM commands by having a single
fixed SMC ID for all PLM commands and keep the PLM header in subsequent
SMC arguments. Also, enhance size of payload argument count to support
maximum payloads in request and response buffers to transmit all the
IPI command properly.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2601caba849bce3f294177b63baa1ad688e3c5bb

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fix(xilinx): fix logic to read ipi response

Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret stat

fix(xilinx): fix logic to read ipi response

Currently, PLM IPI command supports total 8 32-bit payloads. But existing
logic to read IPI response in TF-A is trying to read 9 32-bit payloads
(ret status + 8 ret payloads) in case of IPI_CRC_CHECK enabled which is
incorrect.

So, fix logic to read only 8 32-bit payloads (ret status + 6 ret payloads + CRC)
in case when IPI_CRC_CHECK is enabled and read 7 32-bit payloads
(ret status + 5 ret payloads + CRC) in case when IPI_CRC_CHECK is disabled.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I0abca2f787cc7a66fdd5522e6bd15a9771029071

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fix(corstone1000): remove unused NS_SHARED_RAM region

After enabling additional features in Trusted Services, the size of BL32
image (OP-TEE + Trusted Services SPs) is larger now. To create more spa

fix(corstone1000): remove unused NS_SHARED_RAM region

After enabling additional features in Trusted Services, the size of BL32
image (OP-TEE + Trusted Services SPs) is larger now. To create more space
in secure RAM for BL32 image, this patch removes NS_SHARED_RAM region
which is not currently used by corstone1000 platform.

Change-Id: I1e9468fd2dcb66b4d21fce245097ba51331ec54d
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>

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fix(corstone1000): pass spsr value explicitly

Passes spsr value for BL33 (U-Boot) explicitly between different boot
stages. This information is needed in order to boot properly.

Change-Id: I06b5b75

fix(corstone1000): pass spsr value explicitly

Passes spsr value for BL33 (U-Boot) explicitly between different boot
stages. This information is needed in order to boot properly.

Change-Id: I06b5b750f963f8609e00ff6bf2838bac0f8b7b28
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>

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fix(arm): remove duplicate jumptable entry

Change-Id: I4cc4ef493318372ec0d0531ca3e98196e7065ab9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

feat(arm): add fw handoff support for RESET_TO_BL31

Change-Id: I78f3c5606f0221bb5fc613a973a7d3fe187db35b
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SP

Merge changes from topic "jc/refact_el1_ctx" into integration

* changes:
refactor(cm): convert el1-ctx assembly offset entries to c structure
feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT

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Merge changes from topic "h616_pmics" into integration

* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: ad

Merge changes from topic "h616_pmics" into integration

* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: add support for AXP313 PMIC
feat(allwinner): h616: add I2C PMIC support
refactor(allwinner): h616: prepare for more than one PMIC model

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Merge "feat(rcar3): populate kaslr-seed in next stage DT" into integration

Merge "fix(fvp): add secure uart interrupt in device region" into integration

Merge "build: consolidate directory creation rules" into integration

Merge "feat(fvp): add flash areas for secure partition" into integration

feat(fvp): add flash areas for secure partition

To support UEFI secure variable service,
StandaloneMm which runs in BL32 should know flash areas.
Add flash memory areas and system register region
so

feat(fvp): add flash areas for secure partition

To support UEFI secure variable service,
StandaloneMm which runs in BL32 should know flash areas.
Add flash memory areas and system register region
so that StandaloneMm access to flash storages.

Change-Id: I803bda9664a17a0b978ebff90974eaf5442a91cd
Signed-off-by: levi.yun <yeoreum.yun@arm.com>

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fix(fvp): add secure uart interrupt in device region

OP-TEE enables the use case of a secure interrupt triggered by the UART
driver. This interrupt is routed by FFA_INTERRUPT interface to OP-TEE.
De

fix(fvp): add secure uart interrupt in device region

OP-TEE enables the use case of a secure interrupt triggered by the UART
driver. This interrupt is routed by FFA_INTERRUPT interface to OP-TEE.
Define the UART interrupt in the FF-A device region node.
Without this change, OPTEE panics at the boot with the following:

| I/TC: No non-secure external DT
| I/TC: manifest DT found
| I/TC: OP-TEE version: 4.3.0-23-gfcd8750677db
| I/TC: WARNING: This OP-TEE configuration might be insecure!
| I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
| I/TC: Primary CPU initializing
| E/TC:0 0 assertion '!res' failed at core/drivers/hfic.c:56 <hfic_op_enable>
| E/TC:0 0 Panic at core/kernel/assert.c:28 <_assert_break>
| E/TC:0 0 TEE load address @ 0x6284000

Change-Id: Icddcdfd032315aeee65ba3100f3a6b470a74435d
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

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