xref: /rk3399_ARM-atf/plat/st/stm32mp2/bl2_plat_setup.c (revision fb3314d9e347ac7d269116634cc793b22b8eeae4) 
1 /*
2  * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 #include <cdefs.h>
9 #include <stdint.h>
10 
11 #include <common/debug.h>
12 #include <common/desc_image_load.h>
13 #include <drivers/clk.h>
14 #include <drivers/mmc.h>
15 #include <drivers/st/regulator_fixed.h>
16 #include <drivers/st/stm32mp2_ddr_helpers.h>
17 #include <lib/fconf/fconf.h>
18 #include <lib/fconf/fconf_dyn_cfg_getter.h>
19 #include <lib/mmio.h>
20 #include <lib/xlat_tables/xlat_tables_v2.h>
21 #include <plat/common/platform.h>
22 
23 #include <platform_def.h>
24 #include <stm32mp_common.h>
25 #include <stm32mp_dt.h>
26 
27 #define BOOT_CTX_ADDR	0x0e000020UL
28 
29 static void print_reset_reason(void)
30 {
31 	uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR);
32 
33 	if (rstsr == 0U) {
34 		WARN("Reset reason unknown\n");
35 		return;
36 	}
37 
38 	INFO("Reset reason (0x%x):\n", rstsr);
39 
40 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) {
41 		if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) {
42 			INFO("System exits from Standby for CA35\n");
43 			return;
44 		}
45 
46 		if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) {
47 			INFO("D1 domain exits from DStandby\n");
48 			return;
49 		}
50 	}
51 
52 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) {
53 		INFO("  Power-on Reset (rst_por)\n");
54 		return;
55 	}
56 
57 	if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) {
58 		INFO("  Brownout Reset (rst_bor)\n");
59 		return;
60 	}
61 
62 	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) {
63 		INFO("  System reset (SYSRST) by M33\n");
64 		return;
65 	}
66 
67 	if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) {
68 		INFO("  System reset (SYSRST) by A35\n");
69 		return;
70 	}
71 
72 	if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) {
73 		INFO("  Clock failure on HSE\n");
74 		return;
75 	}
76 
77 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) {
78 		INFO("  IWDG1 system reset (rst_iwdg1)\n");
79 		return;
80 	}
81 
82 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) {
83 		INFO("  IWDG2 system reset (rst_iwdg2)\n");
84 		return;
85 	}
86 
87 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) {
88 		INFO("  IWDG3 system reset (rst_iwdg3)\n");
89 		return;
90 	}
91 
92 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) {
93 		INFO("  IWDG4 system reset (rst_iwdg4)\n");
94 		return;
95 	}
96 
97 	if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) {
98 		INFO("  IWDG5 system reset (rst_iwdg5)\n");
99 		return;
100 	}
101 
102 	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) {
103 		INFO("  A35 processor core 1 reset\n");
104 		return;
105 	}
106 
107 	if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) {
108 		INFO("  Pad Reset from NRST\n");
109 		return;
110 	}
111 
112 	if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) {
113 		INFO("  Reset due to a failure of VDD_CORE\n");
114 		return;
115 	}
116 
117 	if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) {
118 		INFO("  A35 processor reset\n");
119 		return;
120 	}
121 
122 	ERROR("  Unidentified reset reason\n");
123 }
124 
125 void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
126 				  u_register_t arg1 __unused,
127 				  u_register_t arg2 __unused,
128 				  u_register_t arg3 __unused)
129 {
130 	stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR);
131 }
132 
133 void bl2_platform_setup(void)
134 {
135 }
136 
137 static void reset_backup_domain(void)
138 {
139 	uintptr_t pwr_base = stm32mp_pwr_base();
140 	uintptr_t rcc_base = stm32mp_rcc_base();
141 
142 	/*
143 	 * Disable the backup domain write protection.
144 	 * The protection is enable at each reset by hardware
145 	 * and must be disabled by software.
146 	 */
147 	mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P);
148 
149 	while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) {
150 		;
151 	}
152 
153 	/* Reset backup domain on cold boot cases */
154 	if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) {
155 		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
156 
157 		while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) {
158 			;
159 		}
160 
161 		mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
162 	}
163 }
164 
165 void bl2_el3_plat_arch_setup(void)
166 {
167 	const char *board_model;
168 	boot_api_context_t *boot_context =
169 		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
170 
171 	if (stm32_otp_probe() != 0U) {
172 		EARLY_ERROR("OTP probe failed\n");
173 		panic();
174 	}
175 
176 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
177 			BL_CODE_END - BL_CODE_BASE,
178 			MT_CODE | MT_SECURE);
179 
180 	configure_mmu();
181 
182 	if (dt_open_and_check(STM32MP_DTB_BASE) < 0) {
183 		panic();
184 	}
185 
186 	reset_backup_domain();
187 
188 	/*
189 	 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2),
190 	 * and so before stm32mp2_clk_init().
191 	 */
192 	ddr_sub_system_clk_init();
193 
194 	if (stm32mp2_clk_init() < 0) {
195 		panic();
196 	}
197 
198 	stm32_save_boot_info(boot_context);
199 
200 	if (stm32mp_uart_console_setup() != 0) {
201 		goto skip_console_init;
202 	}
203 
204 	stm32mp_print_cpuinfo();
205 
206 	board_model = dt_get_board_model();
207 	if (board_model != NULL) {
208 		NOTICE("Model: %s\n", board_model);
209 	}
210 
211 	stm32mp_print_boardinfo();
212 
213 	print_reset_reason();
214 
215 skip_console_init:
216 	if (fixed_regulator_register() != 0) {
217 		panic();
218 	}
219 
220 	fconf_populate("TB_FW", STM32MP_DTB_BASE);
221 
222 	stm32mp_io_setup();
223 }
224 
225 /*******************************************************************************
226  * This function can be used by the platforms to update/use image
227  * information for given `image_id`.
228  ******************************************************************************/
229 int bl2_plat_handle_post_image_load(unsigned int image_id)
230 {
231 	int err = 0;
232 	bl_mem_params_node_t *bl_mem_params __maybe_unused = get_bl_mem_params_node(image_id);
233 
234 	assert(bl_mem_params != NULL);
235 
236 #if STM32MP_SDMMC || STM32MP_EMMC
237 	/*
238 	 * Invalidate remaining data read from MMC but not flushed by load_image_flush().
239 	 * We take the worst case which is 2 MMC blocks.
240 	 */
241 	if ((image_id != FW_CONFIG_ID) &&
242 	    ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) {
243 		inv_dcache_range(bl_mem_params->image_info.image_base +
244 				 bl_mem_params->image_info.image_size,
245 				 2U * MMC_BLOCK_SIZE);
246 	}
247 #endif /* STM32MP_SDMMC || STM32MP_EMMC */
248 
249 	switch (image_id) {
250 	case FW_CONFIG_ID:
251 		/* Set global DTB info for fixed fw_config information */
252 		set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE,
253 				FW_CONFIG_ID);
254 		fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE);
255 
256 		/*
257 		 * After this step, the BL2 device tree area will be overwritten
258 		 * with BL31 binary, no other data should be read from BL2 DT.
259 		 */
260 
261 		break;
262 
263 	default:
264 		/* Do nothing in default case */
265 		break;
266 	}
267 
268 	return err;
269 }
270