Merge "fix(tc): replace vencoder with simple panel for kernel > 6.6" into integration

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02

fix(tc): replace vencoder with simple panel for kernel > 6.6

The component-aware simple encoder has become outdated with the latest
upstream DRM subsystem changes since Linux kernel commit 4cfe5cc02e3f
("drm/arm/komeda: Remove component framework and add a simple encoder")

To address this we introduce a new compilation flag
`TC_DPU_USE_SIMPLE_PANEL` for control panel vs. encoder enablement.
This flag is set when the kernel version is >= 6.6 and 0 when the kernel
version is < 6.6.

We also rename the `vencoder_in` node to `lcd_in` to avoid unnecessary
conditional code for vencoder vs. simple panel enablement.

Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibb14a56911cfb406b2181a22cc40db58d8ceaa8d

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feat(cpus): add support for Alto CPU

Add basic CPU library code to support the Alto CPU.

Change-Id: I45958be99c4a350a32a9e511d3705fb568b97236
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>

Merge changes I00d2de7b,I5ec82646 into integration

* changes:
feat(tc): fpga: Enable support for loading FIP image to DRAM
feat(tc): allow Android load and Boot From RAM

feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554

feat(tc): fpga: Enable support for loading FIP image to DRAM

This patch enable support for loading FIP image into DRAM rather than
flash drive.

Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loadi

feat(tc): allow Android load and Boot From RAM

This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loading Android image

Change-Id: I5ec82646cb2993e7b5976e702ebcc8efa51d1128
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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Merge changes I04ecd50f,I830b53e2 into integration

* changes:
fix(rcar3-drivers): disable A/B loader support by default
fix(rcar-layout): fix tool build

Merge "chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default" into integration

Merge "feat(tc): increase SCP BL2 size to support optimization 0" into integration

feat(intel): add support for query SDM config error and status

Currently the FPGA reconfig status only return a single error status
which make the debugging of FPGA reconfiguration hard.

This patch

feat(intel): add support for query SDM config error and status

Currently the FPGA reconfig status only return a single error status
which make the debugging of FPGA reconfiguration hard.

This patch is to expose the error status, major error code and
minor error code, for the FPGA reconfig to upper layer app.

Change-Id: I2fc68e30b45ff137f3e52f9569fdf2eaf2ca94ee
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(tc): increase SCP BL2 size to support optimization 0

It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.

Signed-o

feat(tc): increase SCP BL2 size to support optimization 0

It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.

Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib416c89226475d44746a7561dd949a14349c3e4b

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feat(mt8196): add GPIO support

- MT8196 has 271 GPIO pins. Therefore, update id to a proper datatype.
- Add GPIO support for MT8196.

Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I2

feat(mt8196): add GPIO support

- MT8196 has 271 GPIO pins. Therefore, update id to a proper datatype.
- Add GPIO support for MT8196.

Signed-off-by: Cathy Xu <ot_cathy.xu@mediatek.com>
Change-Id: I283939684b54f79d1bba02f38e047e756a56f0c9

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chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default

Previously we only enabled 8GB unless we were loading the filesystem
from RAM.

Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
S

chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default

Previously we only enabled 8GB unless we were loading the filesystem
from RAM.

Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>

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feat(mt8196): initialize platform for MediaTek MT8196

- Add basic platform setup.
- Add MT8196 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add ti

feat(mt8196): initialize platform for MediaTek MT8196

- Add basic platform setup.
- Add MT8196 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add timer driver configuration.

Change-Id: I07fcdeb785fcda4a955c11c39a345da4ad05ef04
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com>

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Merge changes from topic "rd1ae-bl32" into integration

* changes:
feat(rd1ae): add Generic Timer in device tree
docs(rd1ae): update documentation to include BL32
feat(rd1ae): add support for O

Merge changes from topic "rd1ae-bl32" into integration

* changes:
feat(rd1ae): add Generic Timer in device tree
docs(rd1ae): update documentation to include BL32
feat(rd1ae): add support for OP-TEE SPMC

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Merge changes from topic "dtpm_poc" into integration

* changes:
refactor(rpi3): move mbedtls helper to common code
fix(rpi3): use correct name for include guards

Merge changes Ibe44f19e,I9e023edb,I96d655fc into integration

* changes:
build: use parameters in calls to `MAKE_DEP`
build: disable suffix rules globally
build: use full paths for generated li

Merge changes Ibe44f19e,I9e023edb,I96d655fc into integration

* changes:
build: use parameters in calls to `MAKE_DEP`
build: disable suffix rules globally
build: use full paths for generated libraries

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Merge changes I52c84dc2,I9b2a2a11 into integration

* changes:
fix(intel): add FPGA isolation trigger when reconfiguration
fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5

build: disable suffix rules globally

This change centralises the logic that disables the default suffix rules
that Make provides. These rules are a hold-over from legacy standards of
Make, and occas

build: disable suffix rules globally

This change centralises the logic that disables the default suffix rules
that Make provides. These rules are a hold-over from legacy standards of
Make, and occasionally conflict with our rules.

Change-Id: I9e023edbc01b5ae48a96fa1078d0b81faabb0cb9
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build: use full paths for generated libraries

This change modifies the build rules for static libraries so that
individual rules which use those libraries depend directly on the
archive files that a

build: use full paths for generated libraries

This change modifies the build rules for static libraries so that
individual rules which use those libraries depend directly on the
archive files that are generated, rather than their phony target aliases
and `-lX` link flags.

The goal of this is to clean up Make's view of the dependencies between
files, avoiding phony targets (which do not honour timestamps) making
their way into intermediate dependencies.

Change-Id: I96d655fcd94dc259ffa6e8970b2be7b8c7e11123
Signed-off-by: Chris Kay <chris.kay@arm.com>

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refactor(rpi3): move mbedtls helper to common code

In order to support measured boot we need plat_get_mbedtls_heap,
this function currently resides in rpi3_trusted_boot.c, but we do
not need trusted

refactor(rpi3): move mbedtls helper to common code

In order to support measured boot we need plat_get_mbedtls_heap,
this function currently resides in rpi3_trusted_boot.c, but we do
not need trusted board boot to use measured boot, so moving this
to common code removes the need to compile rpi3_trusted_boot.c

Change-Id: I6ac6dfa8c540e456d7cb6932098c921907ad086a
Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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fix(rpi3): use correct name for include guards

fixed rpi_shared.h include guard, previously the commented
endif was RPI3_PRIVATE, which could be a cause for confusion
when searching through header f

fix(rpi3): use correct name for include guards

fixed rpi_shared.h include guard, previously the commented
endif was RPI3_PRIVATE, which could be a cause for confusion
when searching through header files.

Change-Id: I721f9f7c38cd14cda0385593b307cdfc71f810f8
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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feat(qemu): increase size of bl31

Increase BL31 size to have room to spare for debugging with EL3 SPMC.

Change-Id: I6e260a284ed2aa5d515b45be90ee2cdeded9c6a9
Signed-off-by: Jens Wiklander <jens.wikl

feat(qemu): increase size of bl31

Increase BL31 size to have room to spare for debugging with EL3 SPMC.

Change-Id: I6e260a284ed2aa5d515b45be90ee2cdeded9c6a9
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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fix(qemu): fix EL3-SPMC data store alignment

With PLAT=qemu, the EL3-SPMC data store is provided as an array of
uint8_t and implicitly with a 1 byte alignment. But the way the data
store is used it

fix(qemu): fix EL3-SPMC data store alignment

With PLAT=qemu, the EL3-SPMC data store is provided as an array of
uint8_t and implicitly with a 1 byte alignment. But the way the data
store is used it must have a larger alignment, so change to double-word
alignment for maximum compatibility.

Change-Id: I4e9b901889078fee4b87f8333257bdc076386572
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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fix(qemu): fix build error with spmd

Currently when building with PLAT=qemu SPD=spmd SPMC_AT_EL3=1
SPMD_SPM_AT_SEL2=0, there is a build error since
plat_spmd_handle_group0_interrupt() is called irre

fix(qemu): fix build error with spmd

Currently when building with PLAT=qemu SPD=spmd SPMC_AT_EL3=1
SPMD_SPM_AT_SEL2=0, there is a build error since
plat_spmd_handle_group0_interrupt() is called irrespective of
SPMC_AT_EL3. Fix this by making plat_spmd_handle_group0_interrupt()
available if SPD_spmd is defined only.

Change-Id: If5f650d2bd3675cbb4b509e9e3743d3865d7c812
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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