1 /* 2 * Copyright (c) 2024, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <arch_def.h> 14 15 #define PLAT_PRIMARY_CPU (0x0) 16 17 #define MT_GIC_BASE (0x0C400000) 18 #define MCUCFG_BASE (0x0C000000) 19 #define MCUCFG_REG_SIZE (0x50000) 20 #define IO_PHYS (0x10000000) 21 22 /* Aggregate of all devices for MMU mapping */ 23 #define MTK_DEV_RNG1_BASE (IO_PHYS) 24 #define MTK_DEV_RNG1_SIZE (0x10000000) 25 26 #define TOPCKGEN_BASE (IO_PHYS) 27 28 /******************************************************************************* 29 * AUDIO related constants 30 ******************************************************************************/ 31 #define AUDIO_BASE (IO_PHYS + 0x0a110000) 32 33 /******************************************************************************* 34 * SPM related constants 35 ******************************************************************************/ 36 #define SPM_BASE (IO_PHYS + 0x0C004000) 37 38 /******************************************************************************* 39 * UART related constants 40 ******************************************************************************/ 41 #define UART0_BASE (IO_PHYS + 0x06000000) 42 #define UART_BAUDRATE (115200) 43 44 /******************************************************************************* 45 * Infra IOMMU related constants 46 ******************************************************************************/ 47 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 48 #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000) 49 #define PERICFG_AO_BASE (IO_PHYS + 0x06630000) 50 #define PERICFG_AO_REG_SIZE (0x1000) 51 52 /******************************************************************************* 53 * GIC-600 & interrupt handling related constants 54 ******************************************************************************/ 55 /* Base MTK_platform compatible GIC memory map */ 56 #define BASE_GICD_BASE (MT_GIC_BASE) 57 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 58 #define MTK_GIC_REG_SIZE 0x400000 59 60 /******************************************************************************* 61 * MM IOMMU & SMI related constants 62 ******************************************************************************/ 63 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 64 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 65 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 66 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 67 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 68 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 69 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 70 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 71 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 72 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 73 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 74 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 75 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 76 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 77 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 78 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 79 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 80 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 81 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 82 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 83 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 84 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 85 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 86 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 87 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 88 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 89 #define SMI_LARB_REG_RNG_SIZE (0x1000) 90 91 /******************************************************************************* 92 * APMIXEDSYS related constants 93 ******************************************************************************/ 94 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 95 96 /******************************************************************************* 97 * VPPSYS related constants 98 ******************************************************************************/ 99 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 100 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 101 102 /******************************************************************************* 103 * VDOSYS related constants 104 ******************************************************************************/ 105 #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 106 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 107 108 /******************************************************************************* 109 * EMI MPU related constants 110 *******************************************************************************/ 111 #define EMI_MPU_BASE (IO_PHYS + 0x00428000) 112 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000) 113 114 /******************************************************************************* 115 * System counter frequency related constants 116 ******************************************************************************/ 117 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 118 #define SYS_COUNTER_FREQ_IN_MHZ (13) 119 120 /******************************************************************************* 121 * Generic platform constants 122 ******************************************************************************/ 123 #define PLATFORM_STACK_SIZE (0x800) 124 #define SOC_CHIP_ID U(0x8196) 125 126 /******************************************************************************* 127 * Platform memory map related constants 128 ******************************************************************************/ 129 #define TZRAM_BASE (0x94600000) 130 #define TZRAM_SIZE (0x00200000) 131 132 /******************************************************************************* 133 * BL31 specific defines. 134 ******************************************************************************/ 135 /* 136 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 137 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 138 * little space for growth. 139 */ 140 #define BL31_BASE (TZRAM_BASE + 0x1000) 141 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 142 143 /******************************************************************************* 144 * Platform specific page table and MMU setup constants 145 ******************************************************************************/ 146 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 147 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 148 #define MAX_XLAT_TABLES (128) 149 #define MAX_MMAP_REGIONS (512) 150 151 /******************************************************************************* 152 * CPU PM definitions 153 *******************************************************************************/ 154 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 155 #define PLAT_CPU_PM_ILDO_ID (6) 156 #define CPU_IDLE_SRAM_BASE (0x11B000) 157 #define CPU_IDLE_SRAM_SIZE (0x1000) 158 159 /******************************************************************************* 160 * SYSTIMER related definitions 161 ******************************************************************************/ 162 #define SYSTIMER_BASE (0x1C400000) 163 164 #endif /* PLATFORM_DEF_H */ 165