Merge changes from topic "xilinx-versal-net" into integration

* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP s

Merge changes from topic "xilinx-versal-net" into integration

* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC

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feat(versal-net): add support for platform management

Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.

Signed-off-by

feat(versal-net): add support for platform management

Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If2b2941c868bc9b0850d7f3adb81eac0e660c149

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feat(versal-net): add support for IPI

Add support to send IPI to firmware.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I8cd5

feat(versal-net): add support for IPI

Add support to send IPI to firmware.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I8cd54c05b6a726e0d398dfc1cdcc7f4cf09ba725

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feat(versal-net): add SMP support for Versal NET

Add SMP support for Versal NET via register access.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare

feat(versal-net): add SMP support for Versal NET

Add SMP support for Versal NET via register access.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I46d73e2cd678ae720b5255722b6b0611c22659e8

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feat(versal-net): add support for Xilinx Versal NET platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx P

feat(versal-net): add support for Xilinx Versal NET platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410

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fix(zynqmp): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Change-Id: Id85

fix(zynqmp): resolve the misra 4.6 warnings

MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.

Change-Id: Id85e69b29b124052b4a87462ce27fcdfc00c13c9
Signed-off-by: HariBabu Gattem <haribabu.gattem@amd.com>

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Merge "feat(versal): update macro name to generic and move to common place" into integration

Merge changes from topic "provencore-spd" into integration

* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL

Merge changes from topic "provencore-spd" into integration

* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL1 SGIs

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feat(zynqmp): add support for ProvenCore

ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is

feat(zynqmp): add support for ProvenCore

ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is enabled.

Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>
Signed-off-by: Mélanie Favre <melanie.favre@provenrun.com>
Change-Id: I2e36d2983f82fbb9b7acf7e18791b8ed92811b60

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Merge "fix(versal): route GIC IPI interrupts during setup" into integration

Merge "fix(zynqmp): move debug bl31 based address back to OCM" into integration

fix(versal): route GIC IPI interrupts during setup

If primary core is down, then IPI interrupt should be
routed to another core for processing.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Chan

fix(versal): route GIC IPI interrupts during setup

If primary core is down, then IPI interrupt should be
routed to another core for processing.

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I01d7c4232a18c0c3b3f3f9ddadfa6ff5bd2f2471

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Merge changes from topic "xilinx-pm-misc-changes" into integration

* changes:
fix(xilinx): update define for ZynqMP specific functions
fix(xilinx): remove unnecessary header include
fix(xilinx

Merge changes from topic "xilinx-pm-misc-changes" into integration

* changes:
fix(xilinx): update define for ZynqMP specific functions
fix(xilinx): remove unnecessary header include
fix(xilinx): include missing header

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Merge changes from topic "xilinx-misc-changes" into integration

* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): r

Merge changes from topic "xilinx-misc-changes" into integration

* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): remove additional 0x in %p print
fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

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fix(xilinx): update define for ZynqMP specific functions

Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all pl

fix(xilinx): update define for ZynqMP specific functions

Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all platform, define only for ZynqMP.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I45798dadc0f374c5794f517f7d0158675a75caa9

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fix(xilinx): remove unnecessary header include

Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.

Signed-off-by: Rajan Vaja <rajan.va

fix(xilinx): remove unnecessary header include

Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6686757f00370c6ec42b5ee2c44ea5cd13da70c0

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fix(xilinx): include missing header

pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.

Signed-o

fix(xilinx): include missing header

pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic4a6c469c3152e21eaeb365ba96f3a29f14593bf

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chore(zynqmp): fix comment style in zynqmp_def.h

Add missing space in one line comment to follow common coding style.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444e

chore(zynqmp): fix comment style in zynqmp_def.h

Add missing space in one line comment to follow common coding style.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Idebf8f34bf48444ee20a68ac3e6fd7f5a41bf8b0

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chore(versal): add missing dot at the end of sentence

Add missing dot at the end of sentence.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I356e65fd8c572c12795e3492dd02d73f48cb4b67

fix(zynqmp): remove additional 0x in %p print

%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after

fix(zynqmp): remove additional 0x in %p print

%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after fixing
"NOTICE: Can't read DT at 0x100000"

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If83c485a61441f6105d8cbd797f04060dfce2817

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fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and co

fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main

Fix some Misra-C violations. The similar fixes were done by commit
eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and commit
dd1fe7178b57 ("fix(zynqmp): resolve misra R14.4 warnings").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I3ffa92724a09871f7f99c9ac6c326994c165e9bd

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fix(zynqmp): ensure memory write finish with dsb()

GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR

Signed-off-by: Tanmay Shah <tan

fix(zynqmp): ensure memory write finish with dsb()

GICD reg write must complete before core goes to idle
mode. Achieve this with dsb() barrier instruction in IPI
ISR

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: I5af42ca901567ee5e54a5434ebe3e673a92cb9be

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fix(zynqmp): move debug bl31 based address back to OCM

The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM an

fix(zynqmp): move debug bl31 based address back to OCM

The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM and likely
it was typo. Correct default address should be 0xfffe5000. If TF-A size is
bigger please select location DDR which should be fine for DEBUG cases.

Reported-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I055f3a59cdca527f6029fcc2a19d76be35924d24

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feat(versal): update macro name to generic and move to common place

Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.

Signed-of

feat(versal): update macro name to generic and move to common place

Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Acked-by: Tanmay Shah <tanmay.shah@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic3819eea78b6c7b51ffaa13081026dd191b76125

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feat(versal): add infrastructure to handle multiple interrupts

Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infras

feat(versal): add infrastructure to handle multiple interrupts

Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A

Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e

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