| a3b0a342 | 22-May-2024 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(xilinx): register for idle callback
Currently, only Linux registering for getting idle callback during subsystem restart or force power down. Because of that if Linux boot hang or someone wants
fix(xilinx): register for idle callback
Currently, only Linux registering for getting idle callback during subsystem restart or force power down. Because of that if Linux boot hang or someone wants to do subsystem restart before Linux boot then it's not working. So, register for idle callback in TF-A to get idle callback during subsystem restart or force power down to do ARM specific steps for proper power down of core.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: If7c01f79be6958678243be844bcfdc50d59b0fb8
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| 924f8ce2 | 30-May-2024 |
Ronak Jain <ronak.jain@amd.com> |
feat(xilinx): remove PM_IOCTL and PM_QUERY_DATA APIs
Today, the PM_IOCTL and PM_QUERY_DATA APIs are there to maintain backward compatibility. Now, the usage of these APIs on the Linux side and the f
feat(xilinx): remove PM_IOCTL and PM_QUERY_DATA APIs
Today, the PM_IOCTL and PM_QUERY_DATA APIs are there to maintain backward compatibility. Now, the usage of these APIs on the Linux side and the firmware side is updated. Hence remove the deprecated PM_IOCTL and PM_QUERY_DATA EEMI API from the TF-A to make TF-A pass through.
Note: Only use the newer kernel to access the deprecated features in this patch. Otherwise, the system may not function correctly.
Change-Id: I23effb7ff62e7f83563c2b422ea64a0289fd880f Signed-off-by: Ronak Jain <ronak.jain@amd.com>
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| f1464cea | 09-May-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I0e7650c0,I33acead9 into integration
* changes: fix(xilinx): follow MISRA-C standards for condition check fix(zynqmp): resolve null pointer dereferencing |
| af3e8e63 | 21-Feb-2024 |
Salman Nabi <salman.nabi@arm.com> |
refactor(console): consolidate console runtime switch
Refactor console_flush() and console_switch_state(CONSOLE_FLAG_RUNTIME) to bl31_main(). This has been done per the recommendation in TF-A mailin
refactor(console): consolidate console runtime switch
Refactor console_flush() and console_switch_state(CONSOLE_FLAG_RUNTIME) to bl31_main(). This has been done per the recommendation in TF-A mailing list. These calls need to be the last calls, after any runtime initialization has been done, before BL31 exits.
All platforms that override the generic implementation of bl31_plat_runtime_setup() have been refactored. The console_flush() and console_switch_state() calls have been removed as they become part of bl31_main() function.
Any platform that don't need to make any change to the generic (weak) implementation of bl31_plat_runtime_setup() don't need to override it in their platforms.
Change-Id: I6d04d6daa9353daeaa7e3df9e9adf6f322a917b8 Signed-off-by: Salman Nabi <salman.nabi@arm.com>
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| 48932c3c | 19-Feb-2024 |
Salman Nabi <salman.nabi@arm.com> |
refactor(xilinx): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are no lingering chars in the FIFO when we move to the runtime console.
TF-A
refactor(xilinx): console runtime switch on bl31 exit
Flush the FIFO before switching to runtime. This is so that there are no lingering chars in the FIFO when we move to the runtime console.
TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME) and console_flush() calls and make them the last calls in bl31_main() (before BL31 exits). Until then they are being left as the last calls in bl31_plat_runtime_setup() for testing before refactoring.
This patch affects Xilinx SoCs only.
Change-Id: Iea4cf920934bbde4312f40c8c7b3e0f56a316e86 Signed-off-by: Salman Nabi <salman.nabi@arm.com>
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| 655e62aa | 08-May-2024 |
Ronak Jain <ronak.jain@amd.com> |
fix(xilinx): follow MISRA-C standards for condition check
As per the MISRA-C standards, there should be proc == NULL not just !proc.
Fix the same.
Change-Id: I0e7650c09b045882a0235869d7ef9fca27f96
fix(xilinx): follow MISRA-C standards for condition check
As per the MISRA-C standards, there should be proc == NULL not just !proc.
Fix the same.
Change-Id: I0e7650c09b045882a0235869d7ef9fca27f96d9a Signed-off-by: Ronak Jain <ronak.jain@amd.com>
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| 20fa9fc8 | 08-May-2024 |
Ronak Jain <ronak.jain@amd.com> |
fix(zynqmp): resolve null pointer dereferencing
The upstream coverity tool has reported the null pointer dereferences (NULL_RETURNS) warning.
The coverity warning, Dereferencing a pointer that migh
fix(zynqmp): resolve null pointer dereferencing
The upstream coverity tool has reported the null pointer dereferences (NULL_RETURNS) warning.
The coverity warning, Dereferencing a pointer that might be "NULL" "proc" when calling "pm_client_suspend".
Fix the same by checking the NULL before processing further.
Change-Id: I33acead9250bab0ed24b94aa1c1bdc31e80de771 Signed-off-by: Ronak Jain <ronak.jain@amd.com>
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| 48f1bc9f | 02-May-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(zynqmp): remove unused pm_get_proc_by_node()" into integration |
| b03ba480 | 16-Apr-2024 |
Ronak Jain <ronak.jain@amd.com> |
feat(zynqmp): remove unused pm_get_proc_by_node()
The pm_get_proc_by_node() is not used anywhere. Hence remove the same.
Change-Id: Ifd68dd524cae0a9f1684d943019563027859ccea Signed-off-by: Ronak Ja
feat(zynqmp): remove unused pm_get_proc_by_node()
The pm_get_proc_by_node() is not used anywhere. Hence remove the same.
Change-Id: Ifd68dd524cae0a9f1684d943019563027859ccea Signed-off-by: Ronak Jain <ronak.jain@amd.com>
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| 652c1ab1 | 19-Apr-2024 |
Michal Simek <michal.simek@amd.com> |
fix(xilinx): check proc variable before use
Check return value from pm_get_proc() to make sure that CPU is valid.
Signed-off-by: Michal Simek <michal.simek@amd.com> Change-Id: If51b5d42ce87f31fd732
fix(xilinx): check proc variable before use
Check return value from pm_get_proc() to make sure that CPU is valid.
Signed-off-by: Michal Simek <michal.simek@amd.com> Change-Id: If51b5d42ce87f31fd732ab58ae8fcd0e2db0a2a8
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| 9a7f892e | 14-Feb-2024 |
Tanmay Shah <tanmay.shah@amd.com> |
feat(xilinx): send SGI to mailbox driver
Generate SGI to mailbox driver if IPI FIQ occurs due to agents other than PMC.
Change-Id: Ieefb9f0db4009fe0179b18d30da153ce3f9e134c Signed-off-by: Tanmay Sh
feat(xilinx): send SGI to mailbox driver
Generate SGI to mailbox driver if IPI FIQ occurs due to agents other than PMC.
Change-Id: Ieefb9f0db4009fe0179b18d30da153ce3f9e134c Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
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| 1064bc6c | 22-Jan-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "idling-during-subsystem-restart" into integration
* changes: fix(xilinx): add console_flush() before shutdown fix(xilinx): fix sending sgi to linux feat(xilinx): add
Merge changes from topic "idling-during-subsystem-restart" into integration
* changes: fix(xilinx): add console_flush() before shutdown fix(xilinx): fix sending sgi to linux feat(xilinx): add new state to identify cpu power down feat(xilinx): request cpu power down from reset feat(xilinx): power down all cores on receiving cpu pwrdwn req feat(xilinx): add handler for power down req sgi irq feat(xilinx): add wrapper to handle cpu power down req fix(versal-net): use arm common GIC handlers fix(xilinx): rename macros to align with ARM
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| b7e85c7c | 22-Jan-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(versal): extend platform address space sizes" into integration |
| 6a80c20e | 11-Jan-2024 |
Akshay Belsare <akshay.belsare@amd.com> |
fix(xilinx): deprecate SiP service count query
As per SMCCC Section 6.2, the call count query for all the services has been deprecated from SMCCC v1.2 onwards.
Inline with above change, AMD-Xilinx
fix(xilinx): deprecate SiP service count query
As per SMCCC Section 6.2, the call count query for all the services has been deprecated from SMCCC v1.2 onwards.
Inline with above change, AMD-Xilinx SiP service count query has been deprecated and now onwards will return unknown function identifier error.
Change-Id: I296d119d65549fdb01718d08351d255550e4ead0 Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| 663f024f | 10-Jan-2024 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(versal): extend platform address space sizes
The AMD-Xilinx Versal platform, currently only supports the OCM and Low DDR address ranges in both physical and virtual address range. To locate and
feat(versal): extend platform address space sizes
The AMD-Xilinx Versal platform, currently only supports the OCM and Low DDR address ranges in both physical and virtual address range. To locate and execute TF-A from High DDR and HBM address range, expanding the address scope is necessary.
Depending on the BL31_BASE address both the platform physical and virtual space sizes are selected.
Change-Id: I49112bff9eda44d924c5f49ea99aed9a8d5e5774 Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| 7ec53afa | 09-Oct-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(xilinx): add console_flush() before shutdown
Add console_flush() call before shutting down in order to ensure that console output is flushed.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@a
fix(xilinx): add console_flush() before shutdown
Add console_flush() call before shutting down in order to ensure that console output is flushed.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: I5397105d2d7bf317f199b6326593bdb1c3cc75e2
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| 427e46dd | 12-Sep-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(xilinx): fix sending sgi to linux
Currently in Versal NET TF-A writing 32 bits in icc_asgi1r_el1 register to raise SGI to Linux but this register is of 64 bits. Also its writing only CPU number
fix(xilinx): fix sending sgi to linux
Currently in Versal NET TF-A writing 32 bits in icc_asgi1r_el1 register to raise SGI to Linux but this register is of 64 bits. Also its writing only CPU number and SGI number to this register but along with that it needs to write cluster number and other information. Which is not happening currently. So use generic function plat_ic_raise_ns_sgi() to raise SGI to Linux.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: I6f5146c8315a321b705ed2ef79e2dc927b805ffb
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| 59497016 | 12-Sep-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
feat(xilinx): add new state to identify cpu power down
Currently there is only 1 state for CPU idle which is used while CPU power down from Linux CPU idle feature. But CPU power down when firmware s
feat(xilinx): add new state to identify cpu power down
Currently there is only 1 state for CPU idle which is used while CPU power down from Linux CPU idle feature. But CPU power down when firmware send CPU power down request needs new state in self suspend to distinguish in firmware for CPU power down from power down request or CPU power down from Linux CPU idle. So add new state PM_STATE_CPU_OFF to indicate CPU power down from power down request from firmware.
PM_STATE_CPU_OFF state is supported from self-suspend version 3. So added feature check which sends new state in case of new firmware and old state i.e. PM_STATE_CPU_IDLE in case of old firmware.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: I4118e1b813e5f76fca7b7e9ca1cc598715203fb0
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| 88ee0816 | 19-Jun-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
feat(xilinx): request cpu power down from reset
Send subsystem restart notification to firmware when TF-A receives system reset PSCI call. On receiving subsystem restart call, firmware will send CPU
feat(xilinx): request cpu power down from reset
Send subsystem restart notification to firmware when TF-A receives system reset PSCI call. On receiving subsystem restart call, firmware will send CPU idle callback to TF-A for powering down all cores. Wait for CPU idle callback from firmware and raise power down request to all cores after it receives CPU idle callback to power down core.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: I50f417ae228017f38b648740dc90b2e8f1872620
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| c3280df1 | 25-Apr-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
feat(xilinx): power down all cores on receiving cpu pwrdwn req
On receiving CPU power down request from firmware, TF-A raises SGI interrupt to all active cores for entering in power down state. So a
feat(xilinx): power down all cores on receiving cpu pwrdwn req
On receiving CPU power down request from firmware, TF-A raises SGI interrupt to all active cores for entering in power down state. So add support for power down core on receiving CPU power down request. PWRDWN_WAIT_TIMEOUT is the timeout value in milliseconds for the other cores to transition to power down state.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: I29760a2098852c546fa5a1324262a62c3d75b391
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| ade92a64 | 25-Apr-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
feat(xilinx): add handler for power down req sgi irq
On receiving CPU power down callback, TF-A raises SGI interrupt to all active cores to power down each active cores. Add handler for this SGI IRQ
feat(xilinx): add handler for power down req sgi irq
On receiving CPU power down callback, TF-A raises SGI interrupt to all active cores to power down each active cores. Add handler for this SGI IRQ.
By default TF-A uses SGI 6 for CPU power down request. This can be configurable through CPU_PWRDWN_SGI build flag.
e.g., If user wants to use SGI 7 instead of SGI 6 then provide build flag CPU_PWRDWN_SGI=7
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd
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| 3dd118cf | 25-Apr-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
feat(xilinx): add wrapper to handle cpu power down req
Firmware sends CPU power down request to TF-A through NOTIFY_CB callback. It indicates CPU needs to power down.
Add wrapper to handle CPU powe
feat(xilinx): add wrapper to handle cpu power down req
Firmware sends CPU power down request to TF-A through NOTIFY_CB callback. It indicates CPU needs to power down.
Add wrapper to handle CPU power down request from firmware through IPI callback.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: Ic4aff874dd29da057c5ffde1899c7f0e5cdf6733
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| b2259261 | 06-Oct-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(versal-net): use arm common GIC handlers
Currently SGI interrupts are not received in secondary cores because of issue in GIC configuration. In current Versal NET specific GIC functions, redist
fix(versal-net): use arm common GIC handlers
Currently SGI interrupts are not received in secondary cores because of issue in GIC configuration. In current Versal NET specific GIC functions, redistributor configuration is not happening properly. Because of that SGI interrupt from one processor to another processor is not transferring. So, use common GIC handlers which will iterate over all GIC redistributor frames and discovers per cpu redistributor frame. Also, it initializes corresponding interface in GICv3.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: I1433260b8520d6a315fdf5df86bd0688f92d211a
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| 79953190 | 05-Oct-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(xilinx): rename macros to align with ARM
Use generic macro name as per common ARM GIC macro name for Versal and Versal NET.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id:
fix(xilinx): rename macros to align with ARM
Use generic macro name as per common ARM GIC macro name for Versal and Versal NET.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com> Change-Id: I2987ff2f612993fc80979f0179c04d316259ed1d
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| cc3374ac | 20-Dec-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
refactor(xilinx): move plat_get_syscnt_freq2 to common file
The code in the AMD-Xilinx platform for Versal and Versal NET is being refactored to move the plat_get_syscnt_freq2() function to a common
refactor(xilinx): move plat_get_syscnt_freq2 to common file
The code in the AMD-Xilinx platform for Versal and Versal NET is being refactored to move the plat_get_syscnt_freq2() function to a common file. This common function is utilized for obtaining the CPU clock frequency from the platform.
Change-Id: I7a4c3fa43a2941d51cacd259c57b24e545aea848 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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