fix(xilinx): add console_flush() before shutdown

Add console_flush() call before shutting down in order to
ensure that console output is flushed.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@a

fix(xilinx): add console_flush() before shutdown

Add console_flush() call before shutting down in order to
ensure that console output is flushed.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I5397105d2d7bf317f199b6326593bdb1c3cc75e2

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fix(xilinx): fix sending sgi to linux

Currently in Versal NET TF-A writing 32 bits in icc_asgi1r_el1 register
to raise SGI to Linux but this register is of 64 bits. Also its writing
only CPU number

fix(xilinx): fix sending sgi to linux

Currently in Versal NET TF-A writing 32 bits in icc_asgi1r_el1 register
to raise SGI to Linux but this register is of 64 bits. Also its writing
only CPU number and SGI number to this register but along with that it
needs to write cluster number and other information. Which is not happening
currently. So use generic function plat_ic_raise_ns_sgi() to raise SGI to
Linux.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I6f5146c8315a321b705ed2ef79e2dc927b805ffb

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feat(xilinx): add new state to identify cpu power down

Currently there is only 1 state for CPU idle which is used while CPU
power down from Linux CPU idle feature. But CPU power down when firmware
s

feat(xilinx): add new state to identify cpu power down

Currently there is only 1 state for CPU idle which is used while CPU
power down from Linux CPU idle feature. But CPU power down when firmware
send CPU power down request needs new state in self suspend to
distinguish in firmware for CPU power down from power down request or CPU
power down from Linux CPU idle. So add new state PM_STATE_CPU_OFF to
indicate CPU power down from power down request from firmware.

PM_STATE_CPU_OFF state is supported from self-suspend version 3. So
added feature check which sends new state in case of new firmware and
old state i.e. PM_STATE_CPU_IDLE in case of old firmware.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I4118e1b813e5f76fca7b7e9ca1cc598715203fb0

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feat(xilinx): request cpu power down from reset

Send subsystem restart notification to firmware when TF-A receives
system reset PSCI call. On receiving subsystem restart call, firmware
will send CPU

feat(xilinx): request cpu power down from reset

Send subsystem restart notification to firmware when TF-A receives
system reset PSCI call. On receiving subsystem restart call, firmware
will send CPU idle callback to TF-A for powering down all cores. Wait
for CPU idle callback from firmware and raise power down request to
all cores after it receives CPU idle callback to power down core.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I50f417ae228017f38b648740dc90b2e8f1872620

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feat(xilinx): power down all cores on receiving cpu pwrdwn req

On receiving CPU power down request from firmware, TF-A raises SGI
interrupt to all active cores for entering in power down state. So a

feat(xilinx): power down all cores on receiving cpu pwrdwn req

On receiving CPU power down request from firmware, TF-A raises SGI
interrupt to all active cores for entering in power down state. So add support
for power down core on receiving CPU power down request. PWRDWN_WAIT_TIMEOUT
is the timeout value in milliseconds for the other cores to transition to
power down state.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I29760a2098852c546fa5a1324262a62c3d75b391

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feat(xilinx): add handler for power down req sgi irq

On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ

feat(xilinx): add handler for power down req sgi irq

On receiving CPU power down callback, TF-A raises SGI interrupt to all active
cores to power down each active cores. Add handler for this SGI IRQ.

By default TF-A uses SGI 6 for CPU power down request. This can be
configurable through CPU_PWRDWN_SGI build flag.

e.g., If user wants to use SGI 7 instead of SGI 6 then provide build
flag CPU_PWRDWN_SGI=7

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Id0df32187d1de3f0af4486eb4d4930cb3ab01dbd

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feat(xilinx): add wrapper to handle cpu power down req

Firmware sends CPU power down request to TF-A through NOTIFY_CB
callback. It indicates CPU needs to power down.

Add wrapper to handle CPU powe

feat(xilinx): add wrapper to handle cpu power down req

Firmware sends CPU power down request to TF-A through NOTIFY_CB
callback. It indicates CPU needs to power down.

Add wrapper to handle CPU power down request from firmware
through IPI callback.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: Ic4aff874dd29da057c5ffde1899c7f0e5cdf6733

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fix(xilinx): rename macros to align with ARM

Use generic macro name as per common ARM GIC macro name for Versal
and Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id:

fix(xilinx): rename macros to align with ARM

Use generic macro name as per common ARM GIC macro name for Versal
and Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I2987ff2f612993fc80979f0179c04d316259ed1d

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refactor(xilinx): move plat_get_syscnt_freq2 to common file

The code in the AMD-Xilinx platform for Versal and Versal NET is being
refactored to move the plat_get_syscnt_freq2() function to a common

refactor(xilinx): move plat_get_syscnt_freq2 to common file

The code in the AMD-Xilinx platform for Versal and Versal NET is being
refactored to move the plat_get_syscnt_freq2() function to a common
file. This common function is utilized for obtaining the CPU clock
frequency from the platform.

Change-Id: I7a4c3fa43a2941d51cacd259c57b24e545aea848
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(versal): initialize cntfrq_el0 register

The set_cnt_freq() function is introduced to configure the counter
frequency register.If the counter frequency register is zero, it writes
the output of p

fix(versal): initialize cntfrq_el0 register

The set_cnt_freq() function is introduced to configure the counter
frequency register.If the counter frequency register is zero, it writes
the output of plat_get_syscnt_freq2() the cpu_clocks to the counter
frequency register.

According to the design specifications provided for Versal, the
lpd_data.cdo file contains a mask_write operation for register
0xFF140020 (base_frequency_ID_register) to set it to 0x5f5e100,
configuring it for a 100MHz clock frequency.

Reading the value of the IOU_SCNTRS_BASE_FREQ register using
mmio_read_32() to determine the counter frequency. If the counter
frequency is zero, the system will set the default CPU clocks constants
in TF-A and displays message. However, if the counter frequency is
non-zero, the program will return the value stored in the
IOU_SCNTRS_BASE_FREQ register.

The issue lies in dcc_status_timeout(),function verifying timeout
status, particularly within timeout_cnt_us2cnt(), converting
microseconds to counter ticks using read_cntfrq_el0(), which returns
zero. timeout_elapsed() then checks if the current counter from
read_cntpct_el0()exceeds the expiration count, denoting timeout.

After the function set_cnt_freq() writes into the counter frequency
register, the function timeout_cnt_us2cnt() is used to obtain the
appropriate counter ticks. Subsequently, the function timeout_elapsed()
checks whether the current counter value read_cntpct_el0() has
exceeded the specified expiration count. If it has, this indicates
that the timeout has lapsed.

Change-Id: I8f2f4d804b5aefa6f92083d831a5ebfade384294
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(xilinx): update correct return types

Refactor the return types to ensure code correctness and compliance
for DT console.

Change-Id: I11dc3afbe168a78ddc03427df3f5f8d10fe40d40
Signed-off-by: Pras

fix(xilinx): update correct return types

Refactor the return types to ensure code correctness and compliance
for DT console.

Change-Id: I11dc3afbe168a78ddc03427df3f5f8d10fe40d40
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(xilinx): add FIT image check in DT console

With this change, the 'is_valid_dtb()' function has been added,
which checks for the presence of the FDT header, FDT open, and the
'/configurations' pr

fix(xilinx): add FIT image check in DT console

With this change, the 'is_valid_dtb()' function has been added,
which checks for the presence of the FDT header, FDT open, and the
'/configurations' property in the DTB. This property is only available
in FIT images. If the property is present, a warning message is
printed, and the code skips reading console information from the
FIT image. Memory mapping is not necessary because it is called in
the early setup function to collect UART information from the DTB.

Change-Id: I91335a180e7ece2cc0ec9fac4026556c48dd8cc8
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(xilinx): add FIT image check in prepare_dtb

Introduce two new functions: 'is_valid_image()' and 'is_fit_image()'
to enhance the functionality of the system. 'is_valid_image()' will
verify the pr

fix(xilinx): add FIT image check in prepare_dtb

Introduce two new functions: 'is_valid_image()' and 'is_fit_image()'
to enhance the functionality of the system. 'is_valid_image()' will
verify the presence of the FDT header and ensure that the FDT is
open. Meanwhile, 'is_fit_image()' will be responsible for detecting
FIT images. When TF-A is built with a DTB address during compilation
and later executed from DDR memory, TF-A will dynamically reserve a
memory location in the DTB during runtime.

This approach is effective when a raw DTB is present at the specified
address location. With this change, the "is_fit_image()" function
has been introduced to verify the existence of the "/configurations"
property within the DTB.

The presence of this property is exclusive to FIT images. In case
the property is found, a warning message is displayed, and memory
space reservation for its address space in DDR is not performed by
TF-A. However, if the property is not present, TF-A continues its
usual procedure of updating the raw DTB.

Additionally, dynamic mapping has been refactored and separated into
distinct functions: "add_mmap_dynamic_region ()" and
"remove_dynamic_mmap()". This separation enhances compatibility
and maintains better code organization.

Change-Id: I9cd3f09863b44483445e58c802dee34d58dfe2e9
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge "feat(zynqmp): remove pm_ioctl_set_sgmii_mode api" into integration

feat(zynqmp): remove pm_ioctl_set_sgmii_mode api

There are no existing users of pm_ioctl_set_sgmii_mode() API so
cleanup the dead code.

Change-Id: I1088d2f5c944bf54fc5fdd554360bdd321ad798a
Signed-o

feat(zynqmp): remove pm_ioctl_set_sgmii_mode api

There are no existing users of pm_ioctl_set_sgmii_mode() API so
cleanup the dead code.

Change-Id: I1088d2f5c944bf54fc5fdd554360bdd321ad798a
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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feat(versal-net): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal NET platform. TSP is a component for testing and validating
secure OS and trusted execut

feat(versal-net): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal NET platform. TSP is a component for testing and validating
secure OS and trusted execution environments.

If a BL32 image is present, then there must be a matching Secure-EL1
Payload Dispatcher (SPD) service called TSPD, this service is
responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of BL32
once the runtime services are fully initialized. BL31 invokes such
a registered function to initialize BL32 before running BL33.

The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3 This is
because the S-EL1 can use GIC system registers to manage interrupts
and does not need GIC interface base addresses to be configured.

The secure code load address is initially being pointed to 0x0 in the
handoff parameters, which is different from the default or user-provided
load address of 0x60000000. In this case, set up the PC to the
requested BL32_BASE address to ensure that the secure code is loaded
and executed from the correct location.

Change-Id: I58fe256dc9d6be5cee384c5ebb9baca2737c02a6
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(versal): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal platform. TSP is a component for testing and validating
secure OS and trusted execution envi

feat(versal): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal platform. TSP is a component for testing and validating
secure OS and trusted execution environments.

If a BL32 image is present, then there must be a matching Secure-
EL1 Payload Dispatcher (SPD) service called TSPD, this service
is responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of
BL32 once the runtime services are fully initialized. BL31 invokes
such a registered function to initialize BL32 before running BL33.

The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3
This is because the S-EL1 can use GIC system registers to manage
interrupts and does not need GIC interface base addresses to be
configured.

The secure code load address is initially being pointed to 0x0
in the handoff parameters, which is different from the default
or user-provided load address of 0x60000000. In this case, set up
the PC to the requested BL32_BASE address to ensure that the secure
code is loaded and executed from the correct location.

Change-Id: Ida0fc6467a10bfde8927ff9b3755a83f3e16f068
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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refactor(xilinx): add generic TSP makefile

Updated the generic TSP makefile in the common path for reuse in
different platforms.

Change-Id: Idd14675bc547e0a4a95132653a181e7ff39a547a
Signed-off-by:

refactor(xilinx): add generic TSP makefile

Updated the generic TSP makefile in the common path for reuse in
different platforms.

Change-Id: Idd14675bc547e0a4a95132653a181e7ff39a547a
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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chore(zynqmp): reorganize tsp code into common path

Reorganized TSP code into common folder, updated paths in
tsp-zynqmp.mk. Handling the return value of a console registration
function.

Change-Id:

chore(zynqmp): reorganize tsp code into common path

Reorganized TSP code into common folder, updated paths in
tsp-zynqmp.mk. Handling the return value of a console registration
function.

Change-Id: I848f17c3417b3e8c8cbd2058e9642ed13d121325
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(zynqmp): retrieval of console information from dtb

Introduces functionality to retrieve console information from the
device tree (DTB) and use it in TF-A code.

With fdt_get_stdout_node_offset(

feat(zynqmp): retrieval of console information from dtb

Introduces functionality to retrieve console information from the
device tree (DTB) and use it in TF-A code.

With fdt_get_stdout_node_offset() function, which reads the 'secure-chosen'
first,'chosen' and 'stdout-path' properties from the DTB, providing a
convenient and standardized way to access serial console information.

Implemented a comparison mechanism between early console information
and the data populated from the DTB. In case of a mismatch, the commit
takes care of unregistering the build-time console configuration and
registering the DTB-based console.

Reorganizes the console configuration setup in BL31 by moving it to a
dedicated function called setup_console() in the plat_console.c
file. This change improves code readability by isolating
console-related settings, making it easier to manage and extend the
console configuration in the future.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I857042fc0fb8f070bbc11f6b47aa57a72fbe5392

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refactor(xilinx): remove multiple return paths in prepare_dtb

presence of multiple return path in prepare_dtb results in misra c
violation 15.5: this return statement is not the final statement
in t

refactor(xilinx): remove multiple return paths in prepare_dtb

presence of multiple return path in prepare_dtb results in misra c
violation 15.5: this return statement is not the final statement
in the compound statement that forms the body of the function.
prepare_dtb is refactored to address the same.

Change-Id: I17ca4314202d6ca8d6fb0c4ea2ed9d31a152371b
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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fix(xilinx): dcache flush for dtb region

flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related ent

fix(xilinx): dcache flush for dtb region

flush dcache region for dtb so that dtb cache entries are first written
to disk and are invalidated afterwards to avoid presence of any stale
dtb related entry in the dcache.

Change-Id: Ide0ed58f799b35b690ed790c7498ecdc334e02f5
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I411deff57ab141fc2978a2e916aec2d988cb8f9c

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Merge "fix(xilinx): don't reserve 1 more byte" into integration

fix(xilinx): don't reserve 1 more byte

The commit f123b91fddfc ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a5e
("fix(versal-net): fix BLXX memory limits for u

fix(xilinx): don't reserve 1 more byte

The commit f123b91fddfc ("fix(versal): fix BLXX memory
limits for user defined values") and commit a80da3899a5e
("fix(versal-net): fix BLXX memory limits for user defined
values") fixed issue regarding linker alignment section.
But removing -1 logic is not reflected in plat_fdt() memory
reservation code.
That's why remove +1 from prepare_dtb() not to generate a reserved
memory node with bigger size which ends up with reserving more
space than actually requested by a full featured bootloader or OS.

Change-Id: I0a646cee7d5a55157a6eb1b672c2edbe89e6a57f
Signed-off-by: Michal Simek <michal.simek@amd.com>

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