| f577388a | 10-Dec-2020 |
Nishanth Menon <nm@ti.com> |
ti: k3: common: sec_proxy: Fill non-message data fields with 0x0
Sec proxy data buffer is 60 bytes with the last of the registers
indicating transmission completion. This however poses a bit
of a ch
ti: k3: common: sec_proxy: Fill non-message data fields with 0x0
Sec proxy data buffer is 60 bytes with the last of the registers
indicating transmission completion. This however poses a bit
of a challenge.
The backing memory for sec_proxy is regular memory, and all sec proxy
does is to trigger a burst of all 60 bytes of data over to the target
thread backing ring accelerator. It doesn't do a memory scrub when
it moves data out in the burst. When we transmit multiple messages,
remnants of previous message is also transmitted which results in
some random data being set in TISCI fields of messages that have been
expanded forward.
The entire concept of backward compatibility hinges on the fact that
the unused message fields remain 0x0 allowing for 0x0 value to be
specially considered when backward compatibility of message extension
is done.
So, instead of just writing the completion register, we continue
to fill the message buffer up with 0x0 (note: for partial message
involving completion, we already do this).
This allows us to scale and introduce ABI changes back into TF-A only
as needed.
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ie22cb2a319f4aa80aef23ffc7e059207e5d4c640
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| 6a22d9ea | 11-Dec-2020 |
Nishanth Menon <nm@ti.com> |
ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg
ARM's generic timer[1] picks up it's graycode from GTC. However, the
frequency of the GTC is supposed to be programmed in CNTFID0[2]
ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg
ARM's generic timer[1] picks up it's graycode from GTC. However, the
frequency of the GTC is supposed to be programmed in CNTFID0[2]
register.
In K3, architecture, GTC provides a central time to many parts of the
SoC including graycode to the generic timer in the ARMv8 subsystem.
However, due to the central nature and the need to enable the counter
early in the boot process, the R5 based bootloader enables GTC and
programs it's frequency based on central needs of the system. This
may not be a constant 200MHz based on the system. The bootloader is
supposed to program the FID0 register with the correct frequency it
has sourced for GTC from the central system controller, and TF-A is
supposed to use that as the frequency for it's local timer.
A mismatch in programmed frequency and what we program for generic
timer will, as we can imagine, all kind of weird mayhem.
So, check the CNTFID0 register, if it is 0, warn and use the default
frequency to continue the boot process.
While at it, we can also check CNTCR register to provide some basic
diagnostics to make sure that we don't have OS folks scratch their
heads. Even though this is used during cpu online operations, the cost
of this additional check is minimal enough for us not to use #ifdeffery
with DEBUG flags.
[1] https://developer.arm.com/documentation/100095/0002/generic-timer/generic-timer-register-summary/aarch64-generic-timer-register-summary
[2] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntfid0
[3] https://developer.arm.com/docs/ddi0595/h/external-system-registers/cntcr
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: Ib03e06788580f3540dcb1a11677d0d6d398b2c9f
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| 60fba7c8 | 10-Dec-2020 |
Nishanth Menon <nm@ti.com> |
ti: k3: common: Enable A72 erratum 1319367
The CatB erratum ARM_ERRATA_A72_1319367 applies to all TI A72
platforms as well.
See the following for further information:
https://developer.arm.com/docu
ti: k3: common: Enable A72 erratum 1319367
The CatB erratum ARM_ERRATA_A72_1319367 applies to all TI A72
platforms as well.
See the following for further information:
https://developer.arm.com/documentation/epm012079/11/
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I80c6262b9cdadcb12f6dfd5a21272989ba257719
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| 32967a37 | 16-Jan-2020 |
Andrew F. Davis <afd@ti.com> |
ti: k3: drivers: ti_sci: Put sequence number in coherent memory
The current message sequence number is accessed both with caches on and
off so put this memory in the un-cached coherent section so ac
ti: k3: drivers: ti_sci: Put sequence number in coherent memory
The current message sequence number is accessed both with caches on and
off so put this memory in the un-cached coherent section so accesses
are consistent and coherency is maintained.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ieeefefeaffc691e4e4c4de7c74490d50ff9de807
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| 592ede25 | 16-Jan-2020 |
Andrew F. Davis <afd@ti.com> |
ti: k3: drivers: ti_sci: Remove indirect structure of const data
The 'info' structure contained what is only static data for this
implementation of TI-SCI. Remove this indirection and remove the
str
ti: k3: drivers: ti_sci: Remove indirect structure of const data
The 'info' structure contained what is only static data for this
implementation of TI-SCI. Remove this indirection and remove the
struct.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I2328fddf388bf7d56a56bd673c080e78c86fe072
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| 586621f1 | 11-Feb-2019 |
Andrew F. Davis <afd@ti.com> |
ti: k3: common: Enable ARM cluster power down
When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sendi
ti: k3: common: Enable ARM cluster power down
When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sending the cluster power down sequence to the system
power controller firmware.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216
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| 48d6b264 | 25-Apr-2019 |
Andrew F. Davis <afd@ti.com> |
ti: k3: common: Remove coherency workaround for AM65x
We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the las
ti: k3: common: Remove coherency workaround for AM65x
We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.
Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>
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| 16a755f3 | 10-May-2019 |
Andrew F. Davis <afd@ti.com> |
ti: k3: common: Set L2 latency on A72 cores
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency h
ti: k3: common: Set L2 latency on A72 cores
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a
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