stm32mp1: SCMI clock and reset service in SP_MIN

This change implements platform services for stm32mp1 to expose clock
and reset controllers over SCMI clock and reset domain protocols
in sp_min firm

stm32mp1: SCMI clock and reset service in SP_MIN

This change implements platform services for stm32mp1 to expose clock
and reset controllers over SCMI clock and reset domain protocols
in sp_min firmware.

Requests execution use a fastcall SMC context using a SiP function ID.
The setup allows the create SCMI channels by assigning a specific
SiP SMC function ID for each channel/agent identifier defined. In this
change, stm32mp1 exposes a single channel and hence expects single
agent at a time.

The input payload in copied in secure memory before the message
in passed through the SCMI server drivers. BL32/sp_min is invoked
for a single SCMI message processing and always returns with a
synchronous response message passed back to the caller agent.

This change fixes and updates STM32_COMMON_SIP_NUM_CALLS that was
previously wrongly set 4 whereas only 1 SiP SMC function ID was to
be counted. STM32_COMMON_SIP_NUM_CALLS is now set to 3 since the
2 added SiP SMC function IDs for SCMI services.

Change-Id: Icb428775856b9aec00538172aea4cf11e609b033
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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Merge "stm32mp1: register shared resource per IOMEM address" into integration

stm32mp1: register shared resource per IOMEM address

Introduce helper functions stm32mp_register_secure_periph_iomem()
and stm32mp_register_non_secure_periph_iomem() for drivers to
register a resour

stm32mp1: register shared resource per IOMEM address

Introduce helper functions stm32mp_register_secure_periph_iomem()
and stm32mp_register_non_secure_periph_iomem() for drivers to
register a resource as secure or non-secure based on its SoC
interface registers base address.

These functions are stubbed when shared resources driver is not
embedded (!STM32MP_SHARED_RESOURCES) so that drivers embedded
in other BL stages do not bother whether they shall register or
not their resources.

Change-Id: Icebd05a930afc5964bc4677357da5d1b23666066
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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Merge changes from topic "stm32-shres" into integration

* changes:
stm32mp1: shared resources: apply registered configuration
stm32mp1: shared resources: count GPIOZ bank pins
stm32mp1: shared

Merge changes from topic "stm32-shres" into integration

* changes:
stm32mp1: shared resources: apply registered configuration
stm32mp1: shared resources: count GPIOZ bank pins
stm32mp1: shared resources: define resource identifiers

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Merge "stm32mp1: use last page of SYSRAM as SCMI shared memory" into integration

stm32mp1: use last page of SYSRAM as SCMI shared memory

SCMI shared memory is used to exchange message payloads between
secure SCMI services and non-secure SCMI agents. It is mapped
uncached (device

stm32mp1: use last page of SYSRAM as SCMI shared memory

SCMI shared memory is used to exchange message payloads between
secure SCMI services and non-secure SCMI agents. It is mapped
uncached (device) mainly to conform to existing support in
the Linux kernel. Note that executive messages are mostly short
(few 32bit words) hence not using cache will not penalize much
performances.

Platform stm32mp1 shall configure ETZPC to harden properly the
secure and non-secure areas of the SYSRAM address space, that before
CPU accesses the shared memory when mapped non-secure.

This change defines STM32MP_SEC_SYSRAM_BASE/STM32MP_SEC_SYSRAM_SIZE and
STM32MP_NS_SYSRAM_BASE/STM32MP_NS_SYSRAM_SIZE.

Change-Id: I71ff02a359b9668ae1c5a71b5f102cf3d310f289
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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stm32mp1: shared resources: define resource identifiers

Define enum stm32mp_shres for platform stm32mp1. The enumerated
type defines all resources that can be assigned to secure or
non-secure worlds

stm32mp1: shared resources: define resource identifiers

Define enum stm32mp_shres for platform stm32mp1. The enumerated
type defines all resources that can be assigned to secure or
non-secure worlds at run time for the platform.

Change-Id: I5de20d72735856645f1efd0993643278e8d35bcb
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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Merge changes from topic "stm32-etzpc" into integration

* changes:
plat/stm32mp1: sp_min relies on etzpc driver
dts: stm32mp157c: add etzpc node
drivers: introduce ST ETZPC driver

plat/stm32mp1: sp_min relies on etzpc driver

Use ETZPC driver to configure secure aware interfaces to assign
them to non-secure world. Sp_min also configures BootROM resources
and SYSRAM to assign b

plat/stm32mp1: sp_min relies on etzpc driver

Use ETZPC driver to configure secure aware interfaces to assign
them to non-secure world. Sp_min also configures BootROM resources
and SYSRAM to assign both to secure world only.

Define stm32mp15 SoC identifiers for the platform specific DECPROT
instances.

Change-Id: I3bec9f47b04bcba3929e4df886ddb1d5ff843089
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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Merge changes from topic "ddr_map" into integration

* changes:
stm32mp1: use stm32mp_get_ddr_ns_size() function
stm32mp1: set XN attribute for some areas in BL2
stm32mp1: dynamically map DDR l

Merge changes from topic "ddr_map" into integration

* changes:
stm32mp1: use stm32mp_get_ddr_ns_size() function
stm32mp1: set XN attribute for some areas in BL2
stm32mp1: dynamically map DDR later and non-cacheable during its test
stm32mp1: add a function to get non-secure DDR size

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stm32mp1: add a function to get non-secure DDR size

This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT

stm32mp1: add a function to get non-secure DDR size

This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT values fits the default DDR range.
This non-secure memory is available for BL33 and non-secure OS.

Change-Id: I162ae5e990a0f9b6b7d07e539de029f1d61a391b
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge "Enable -Wredundant-decls warning check" into integration

Enable -Wredundant-decls warning check

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently,

Enable -Wredundant-decls warning check

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge changes from topic "ld/mtd_framework" into integration

* changes:
doc: stm32mp1: Update build command line
fdts: stm32mp1: remove second QSPI flash instance
stm32mp1: Add support for SPI

Merge changes from topic "ld/mtd_framework" into integration

* changes:
doc: stm32mp1: Update build command line
fdts: stm32mp1: remove second QSPI flash instance
stm32mp1: Add support for SPI-NOR boot device
stm32mp1: Add support for SPI-NAND boot device
spi: stm32_qspi: Add QSPI support
fdts: stm32mp1: update for FMC2 pin muxing
stm32mp1: Add support for raw NAND boot device
fmc: stm32_fmc2_nand: Add FMC2 driver support
stm32mp1: Reduce MAX_XLAT_TABLES to 4
io: stm32image: fix device_size type
stm32mp: add DT helper for reg by name
stm32mp1: add compilation flags for boot devices
lib: utils_def: add CLAMP macro
compiler_rt: Import popcountdi2.c and popcountsi2.c files
Add SPI-NOR framework
Add SPI-NAND framework
Add SPI-MEM framework
Add raw NAND framework

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stm32mp1: Add support for SPI-NOR boot device

STM32MP1 platform is able to boot from SPI-NOR devices.
These modifications add this support using the new
SPI-NOR framework.

Change-Id: I75ff9eba4661f

stm32mp1: Add support for SPI-NOR boot device

STM32MP1 platform is able to boot from SPI-NOR devices.
These modifications add this support using the new
SPI-NOR framework.

Change-Id: I75ff9eba4661f9fb87ce24ced2bacbf8558ebe44
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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stm32mp1: Add support for SPI-NAND boot device

STM32MP1 platform is able to boot from SPI-NAND devices.
These modifications add this support using the new
SPI-NAND framework.

Change-Id: I0d5448bdc4

stm32mp1: Add support for SPI-NAND boot device

STM32MP1 platform is able to boot from SPI-NAND devices.
These modifications add this support using the new
SPI-NAND framework.

Change-Id: I0d5448bdc4bde153c1209e8043846c0f935ae5ba
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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stm32mp1: Add support for raw NAND boot device

STM32MP1 platform is able to boot from raw NAND devices.
These modifications add this support using the new
raw NAND framework.

Change-Id: I9e9c2b0393

stm32mp1: Add support for raw NAND boot device

STM32MP1 platform is able to boot from raw NAND devices.
These modifications add this support using the new
raw NAND framework.

Change-Id: I9e9c2b03930f98a5ac23f2b6b41945bef43e5043
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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stm32mp1: Reduce MAX_XLAT_TABLES to 4

For STM32MP1, the address space is 4GB, which can be first divided
in 4 parts of 1GB. This LVL1 table is already mapped regardless
of MAX_XLAT_TABLES.
Fixing ty

stm32mp1: Reduce MAX_XLAT_TABLES to 4

For STM32MP1, the address space is 4GB, which can be first divided
in 4 parts of 1GB. This LVL1 table is already mapped regardless
of MAX_XLAT_TABLES.
Fixing typo: Replace Ko to KB.

BL2/sp_min for platform STM32MP1 requires 4 MMU translation tables:
- a level2 table and a level3 table for identity mapped SYSRAM
- a level2 table mapping 2MB of BootROM runtime resources
- a level2 table mapping 2MB of secure DDR (case BL32 is OP-TEE)

Change-Id: If80cbd4fccc7689b39dd540d6649b1313557f326
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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Merge changes from topic "ld/stm32-authentication" into integration

* changes:
stm32mp1: add authentication support for stm32image
bsec: move bsec_mode_is_closed_device() service to platform
c

Merge changes from topic "ld/stm32-authentication" into integration

* changes:
stm32mp1: add authentication support for stm32image
bsec: move bsec_mode_is_closed_device() service to platform
crypto: stm32_hash: Add HASH driver

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stm32mp1: add authentication support for stm32image

This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates

stm32mp1: add authentication support for stm32image

This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates the next loaded STM32 images.
It also enables the dynamic translation table support
(PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51

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Merge changes from topic "yg/stm32mp1_wdg_updates" into integration

* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1:

Merge changes from topic "yg/stm32mp1_wdg_updates" into integration

* changes:
mmc: stm32_sdmmc2: correctly manage block size
mmc: stm32_sdmmc2: manage max-frequency property from DT
stm32mp1: move check_header() to common code
stm32mp1: keep console during runtime
stm32mp1: sp_min: initialize MMU and cache earlier
stm32mp1: add support for LpDDR3
stm32mp1: use a common function to check spinlock is available
clk: stm32mp: enable RTCAPB clock for dual-core chips
stm32mp1: check if the SoC is single core
stm32mp1: print information about board
stm32mp1: print information about SoC
stm32mp1: add watchdog support

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stm32mp1: add support for LpDDR3

This change enables LpDDR3 initialization with PMIC.

Change-Id: I2409a808335dfacd69a8517cb8510cee98bb8161
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: print information about board

On STMicroelectronics boards, the board information is stored in OTP.
This OTP is described in device tree, in BSEC board_id node.

Change-Id: Ieccbdcb0483436

stm32mp1: print information about board

On STMicroelectronics boards, the board information is stored in OTP.
This OTP is described in device tree, in BSEC board_id node.

Change-Id: Ieccbdcb048343680faac8dc577b75c67ac106f5b
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

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stm32mp1: print information about SoC

This information is located in DBGMCU registers.

Change-Id: I480aa046fed9992e3d9665b1f0520bc4b6cfdf30
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32mp1: add watchdog support

Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is

stm32mp1: add watchdog support

Introduce driver for STM32 IWDG peripheral (Independent Watchdog).
It is configured according to device tree content and should be enabled
from there.
The watchdog is not started by default. It can be started after an HW
reset if the dedicated OTP is fused.

The watchdog also needs to be frozen if a debugger is attached.
This is done by configuring the correct bits in DBGMCU.
This configuration is allowed by checking BSEC properties.

An increase of BL2 size is also required when adding this new code.

Change-Id: Ide7535d717885ce2f9c387cf17afd8b5607f3e7f
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>

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