1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_common.h> 23 #include <stm32mp_dt.h> 24 #include <stm32mp_shres_helpers.h> 25 #include <stm32mp1_private.h> 26 #endif 27 28 /******************************************************************************* 29 * STM32MP1 memory map related constants 30 ******************************************************************************/ 31 32 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 33 #define STM32MP_SYSRAM_SIZE U(0x00040000) 34 35 /* DDR configuration */ 36 #define STM32MP_DDR_BASE U(0xC0000000) 37 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 38 #ifdef AARCH32_SP_OPTEE 39 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 40 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 41 #endif 42 43 /* DDR power initializations */ 44 #ifndef __ASSEMBLER__ 45 enum ddr_type { 46 STM32MP_DDR3, 47 STM32MP_LPDDR2, 48 }; 49 #endif 50 51 /* Section used inside TF binaries */ 52 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 53 /* 256 Octets reserved for header */ 54 #define STM32MP_HEADER_SIZE U(0x00000100) 55 56 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 57 STM32MP_PARAM_LOAD_SIZE + \ 58 STM32MP_HEADER_SIZE) 59 60 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 61 (STM32MP_PARAM_LOAD_SIZE + \ 62 STM32MP_HEADER_SIZE)) 63 64 #ifdef AARCH32_SP_OPTEE 65 #define STM32MP_BL32_SIZE U(0) 66 67 #define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE 68 69 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 70 STM32MP_OPTEE_BASE) 71 #else 72 #if STACK_PROTECTOR_ENABLED 73 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 74 #else 75 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 76 #endif 77 #endif 78 79 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 80 STM32MP_SYSRAM_SIZE - \ 81 STM32MP_BL32_SIZE) 82 83 #ifdef AARCH32_SP_OPTEE 84 #if STACK_PROTECTOR_ENABLED 85 #define STM32MP_BL2_SIZE U(0x00019000) /* 100 Ko for BL2 */ 86 #else 87 #define STM32MP_BL2_SIZE U(0x00017000) /* 92 Ko for BL2 */ 88 #endif 89 #else 90 #if STACK_PROTECTOR_ENABLED 91 #define STM32MP_BL2_SIZE U(0x00018000) /* 96 Ko for BL2 */ 92 #else 93 #define STM32MP_BL2_SIZE U(0x00016000) /* 88 Ko for BL2 */ 94 #endif 95 #endif 96 97 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 98 STM32MP_BL2_SIZE) 99 100 /* BL2 and BL32/sp_min require 5 tables */ 101 #define MAX_XLAT_TABLES 5 102 103 /* 104 * MAX_MMAP_REGIONS is usually: 105 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 106 */ 107 #if defined(IMAGE_BL2) 108 #define MAX_MMAP_REGIONS 11 109 #endif 110 #if defined(IMAGE_BL32) 111 #define MAX_MMAP_REGIONS 6 112 #endif 113 114 /* DTB initialization value */ 115 #define STM32MP_DTB_SIZE U(0x00005000) /* 20Ko for DTB */ 116 117 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 118 STM32MP_DTB_SIZE) 119 120 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 121 122 /******************************************************************************* 123 * STM32MP1 device/io map related constants (used for MMU) 124 ******************************************************************************/ 125 #define STM32MP1_DEVICE1_BASE U(0x40000000) 126 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 127 128 #define STM32MP1_DEVICE2_BASE U(0x80000000) 129 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 130 131 /******************************************************************************* 132 * STM32MP1 RCC 133 ******************************************************************************/ 134 #define RCC_BASE U(0x50000000) 135 136 /******************************************************************************* 137 * STM32MP1 PWR 138 ******************************************************************************/ 139 #define PWR_BASE U(0x50001000) 140 141 /******************************************************************************* 142 * STM32MP1 GPIO 143 ******************************************************************************/ 144 #define GPIOA_BASE U(0x50002000) 145 #define GPIOB_BASE U(0x50003000) 146 #define GPIOC_BASE U(0x50004000) 147 #define GPIOD_BASE U(0x50005000) 148 #define GPIOE_BASE U(0x50006000) 149 #define GPIOF_BASE U(0x50007000) 150 #define GPIOG_BASE U(0x50008000) 151 #define GPIOH_BASE U(0x50009000) 152 #define GPIOI_BASE U(0x5000A000) 153 #define GPIOJ_BASE U(0x5000B000) 154 #define GPIOK_BASE U(0x5000C000) 155 #define GPIOZ_BASE U(0x54004000) 156 #define GPIO_BANK_OFFSET U(0x1000) 157 158 /* Bank IDs used in GPIO driver API */ 159 #define GPIO_BANK_A U(0) 160 #define GPIO_BANK_B U(1) 161 #define GPIO_BANK_C U(2) 162 #define GPIO_BANK_D U(3) 163 #define GPIO_BANK_E U(4) 164 #define GPIO_BANK_F U(5) 165 #define GPIO_BANK_G U(6) 166 #define GPIO_BANK_H U(7) 167 #define GPIO_BANK_I U(8) 168 #define GPIO_BANK_J U(9) 169 #define GPIO_BANK_K U(10) 170 #define GPIO_BANK_Z U(25) 171 172 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 173 174 /******************************************************************************* 175 * STM32MP1 UART 176 ******************************************************************************/ 177 #define USART1_BASE U(0x5C000000) 178 #define USART2_BASE U(0x4000E000) 179 #define USART3_BASE U(0x4000F000) 180 #define UART4_BASE U(0x40010000) 181 #define UART5_BASE U(0x40011000) 182 #define USART6_BASE U(0x44003000) 183 #define UART7_BASE U(0x40018000) 184 #define UART8_BASE U(0x40019000) 185 #define STM32MP_UART_BAUDRATE U(115200) 186 187 /* For UART crash console */ 188 #define STM32MP_DEBUG_USART_BASE UART4_BASE 189 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 190 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 191 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 192 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 193 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 194 #define DEBUG_UART_TX_GPIO_PORT 11 195 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 196 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 197 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 198 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 199 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 200 201 /******************************************************************************* 202 * STM32MP1 TZC (TZ400) 203 ******************************************************************************/ 204 #define STM32MP1_TZC_BASE U(0x5C006000) 205 206 #define STM32MP1_TZC_A7_ID U(0) 207 #define STM32MP1_TZC_M4_ID U(1) 208 #define STM32MP1_TZC_LCD_ID U(3) 209 #define STM32MP1_TZC_GPU_ID U(4) 210 #define STM32MP1_TZC_MDMA_ID U(5) 211 #define STM32MP1_TZC_DMA_ID U(6) 212 #define STM32MP1_TZC_USB_HOST_ID U(7) 213 #define STM32MP1_TZC_USB_OTG_ID U(8) 214 #define STM32MP1_TZC_SDMMC_ID U(9) 215 #define STM32MP1_TZC_ETH_ID U(10) 216 #define STM32MP1_TZC_DAP_ID U(15) 217 218 #define STM32MP1_FILTER_BIT_ALL U(3) 219 220 /******************************************************************************* 221 * STM32MP1 SDMMC 222 ******************************************************************************/ 223 #define STM32MP_SDMMC1_BASE U(0x58005000) 224 #define STM32MP_SDMMC2_BASE U(0x58007000) 225 #define STM32MP_SDMMC3_BASE U(0x48004000) 226 227 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 228 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 229 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 230 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 231 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 232 233 /******************************************************************************* 234 * STM32MP1 BSEC / OTP 235 ******************************************************************************/ 236 #define STM32MP1_OTP_MAX_ID 0x5FU 237 #define STM32MP1_UPPER_OTP_START 0x20U 238 239 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 240 241 /* OTP offsets */ 242 #define DATA0_OTP U(0) 243 #define HW2_OTP U(18) 244 245 /* OTP mask */ 246 /* DATA0 */ 247 #define DATA0_OTP_SECURED BIT(6) 248 249 /* IWDG OTP */ 250 #define HW2_OTP_IWDG_HW_POS U(3) 251 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 252 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 253 254 /* HW2 OTP */ 255 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 256 257 /******************************************************************************* 258 * STM32MP1 TAMP 259 ******************************************************************************/ 260 #define TAMP_BASE U(0x5C00A000) 261 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 262 263 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 264 static inline uint32_t tamp_bkpr(uint32_t idx) 265 { 266 return TAMP_BKP_REGISTER_BASE + (idx << 2); 267 } 268 #endif 269 270 /******************************************************************************* 271 * STM32MP1 DDRCTRL 272 ******************************************************************************/ 273 #define DDRCTRL_BASE U(0x5A003000) 274 275 /******************************************************************************* 276 * STM32MP1 DDRPHYC 277 ******************************************************************************/ 278 #define DDRPHYC_BASE U(0x5A004000) 279 280 /******************************************************************************* 281 * STM32MP1 IWDG 282 ******************************************************************************/ 283 #define IWDG_MAX_INSTANCE U(2) 284 #define IWDG1_INST U(0) 285 #define IWDG2_INST U(1) 286 287 #define IWDG1_BASE U(0x5C003000) 288 #define IWDG2_BASE U(0x5A002000) 289 290 /******************************************************************************* 291 * STM32MP1 I2C4 292 ******************************************************************************/ 293 #define I2C4_BASE U(0x5C002000) 294 295 /******************************************************************************* 296 * STM32MP1 DBGMCU 297 ******************************************************************************/ 298 #define DBGMCU_BASE U(0x50081000) 299 300 /******************************************************************************* 301 * Device Tree defines 302 ******************************************************************************/ 303 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 304 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 305 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 306 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 307 308 #endif /* STM32MP1_DEF_H */ 309