1 /* 2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP1_DEF_H 8 #define STM32MP1_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <drivers/st/stm32mp1_rcc.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <lib/utils_def.h> 15 #include <lib/xlat_tables/xlat_tables_defs.h> 16 17 #ifndef __ASSEMBLER__ 18 #include <drivers/st/bsec.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 21 #include <boot_api.h> 22 #include <stm32mp_common.h> 23 #include <stm32mp_dt.h> 24 #include <stm32mp_shres_helpers.h> 25 #include <stm32mp1_dbgmcu.h> 26 #include <stm32mp1_private.h> 27 #endif 28 29 /******************************************************************************* 30 * CHIP ID 31 ******************************************************************************/ 32 #define STM32MP157C_PART_NB U(0x05000000) 33 #define STM32MP157A_PART_NB U(0x05000001) 34 #define STM32MP153C_PART_NB U(0x05000024) 35 #define STM32MP153A_PART_NB U(0x05000025) 36 #define STM32MP151C_PART_NB U(0x0500002E) 37 #define STM32MP151A_PART_NB U(0x0500002F) 38 39 #define STM32MP1_REV_B U(0x2000) 40 41 /******************************************************************************* 42 * PACKAGE ID 43 ******************************************************************************/ 44 #define PKG_AA_LFBGA448 U(4) 45 #define PKG_AB_LFBGA354 U(3) 46 #define PKG_AC_TFBGA361 U(2) 47 #define PKG_AD_TFBGA257 U(1) 48 49 /******************************************************************************* 50 * STM32MP1 memory map related constants 51 ******************************************************************************/ 52 53 #define STM32MP_SYSRAM_BASE U(0x2FFC0000) 54 #define STM32MP_SYSRAM_SIZE U(0x00040000) 55 56 /* DDR configuration */ 57 #define STM32MP_DDR_BASE U(0xC0000000) 58 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */ 59 #ifdef AARCH32_SP_OPTEE 60 #define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */ 61 #define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */ 62 #endif 63 64 /* DDR power initializations */ 65 #ifndef __ASSEMBLER__ 66 enum ddr_type { 67 STM32MP_DDR3, 68 STM32MP_LPDDR2, 69 }; 70 #endif 71 72 /* Section used inside TF binaries */ 73 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 Ko for param */ 74 /* 256 Octets reserved for header */ 75 #define STM32MP_HEADER_SIZE U(0x00000100) 76 77 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 78 STM32MP_PARAM_LOAD_SIZE + \ 79 STM32MP_HEADER_SIZE) 80 81 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 82 (STM32MP_PARAM_LOAD_SIZE + \ 83 STM32MP_HEADER_SIZE)) 84 85 #ifdef AARCH32_SP_OPTEE 86 #define STM32MP_BL32_SIZE U(0) 87 88 #define STM32MP_OPTEE_BASE STM32MP_SYSRAM_BASE 89 90 #define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \ 91 STM32MP_OPTEE_BASE) 92 #else 93 #if STACK_PROTECTOR_ENABLED 94 #define STM32MP_BL32_SIZE U(0x00012000) /* 72 Ko for BL32 */ 95 #else 96 #define STM32MP_BL32_SIZE U(0x00011000) /* 68 Ko for BL32 */ 97 #endif 98 #endif 99 100 #define STM32MP_BL32_BASE (STM32MP_SYSRAM_BASE + \ 101 STM32MP_SYSRAM_SIZE - \ 102 STM32MP_BL32_SIZE) 103 104 #ifdef AARCH32_SP_OPTEE 105 #if STACK_PROTECTOR_ENABLED 106 #define STM32MP_BL2_SIZE U(0x00019000) /* 100 Ko for BL2 */ 107 #else 108 #define STM32MP_BL2_SIZE U(0x00017000) /* 92 Ko for BL2 */ 109 #endif 110 #else 111 #if STACK_PROTECTOR_ENABLED 112 #define STM32MP_BL2_SIZE U(0x00018000) /* 96 Ko for BL2 */ 113 #else 114 #define STM32MP_BL2_SIZE U(0x00016000) /* 88 Ko for BL2 */ 115 #endif 116 #endif 117 118 #define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \ 119 STM32MP_BL2_SIZE) 120 121 /* BL2 and BL32/sp_min require 5 tables */ 122 #define MAX_XLAT_TABLES 5 123 124 /* 125 * MAX_MMAP_REGIONS is usually: 126 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup 127 */ 128 #if defined(IMAGE_BL2) 129 #define MAX_MMAP_REGIONS 11 130 #endif 131 #if defined(IMAGE_BL32) 132 #define MAX_MMAP_REGIONS 6 133 #endif 134 135 /* DTB initialization value */ 136 #define STM32MP_DTB_SIZE U(0x00005000) /* 20Ko for DTB */ 137 138 #define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \ 139 STM32MP_DTB_SIZE) 140 141 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000)) 142 143 /******************************************************************************* 144 * STM32MP1 device/io map related constants (used for MMU) 145 ******************************************************************************/ 146 #define STM32MP1_DEVICE1_BASE U(0x40000000) 147 #define STM32MP1_DEVICE1_SIZE U(0x40000000) 148 149 #define STM32MP1_DEVICE2_BASE U(0x80000000) 150 #define STM32MP1_DEVICE2_SIZE U(0x40000000) 151 152 /******************************************************************************* 153 * STM32MP1 RCC 154 ******************************************************************************/ 155 #define RCC_BASE U(0x50000000) 156 157 /******************************************************************************* 158 * STM32MP1 PWR 159 ******************************************************************************/ 160 #define PWR_BASE U(0x50001000) 161 162 /******************************************************************************* 163 * STM32MP1 GPIO 164 ******************************************************************************/ 165 #define GPIOA_BASE U(0x50002000) 166 #define GPIOB_BASE U(0x50003000) 167 #define GPIOC_BASE U(0x50004000) 168 #define GPIOD_BASE U(0x50005000) 169 #define GPIOE_BASE U(0x50006000) 170 #define GPIOF_BASE U(0x50007000) 171 #define GPIOG_BASE U(0x50008000) 172 #define GPIOH_BASE U(0x50009000) 173 #define GPIOI_BASE U(0x5000A000) 174 #define GPIOJ_BASE U(0x5000B000) 175 #define GPIOK_BASE U(0x5000C000) 176 #define GPIOZ_BASE U(0x54004000) 177 #define GPIO_BANK_OFFSET U(0x1000) 178 179 /* Bank IDs used in GPIO driver API */ 180 #define GPIO_BANK_A U(0) 181 #define GPIO_BANK_B U(1) 182 #define GPIO_BANK_C U(2) 183 #define GPIO_BANK_D U(3) 184 #define GPIO_BANK_E U(4) 185 #define GPIO_BANK_F U(5) 186 #define GPIO_BANK_G U(6) 187 #define GPIO_BANK_H U(7) 188 #define GPIO_BANK_I U(8) 189 #define GPIO_BANK_J U(9) 190 #define GPIO_BANK_K U(10) 191 #define GPIO_BANK_Z U(25) 192 193 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 194 195 /******************************************************************************* 196 * STM32MP1 UART 197 ******************************************************************************/ 198 #define USART1_BASE U(0x5C000000) 199 #define USART2_BASE U(0x4000E000) 200 #define USART3_BASE U(0x4000F000) 201 #define UART4_BASE U(0x40010000) 202 #define UART5_BASE U(0x40011000) 203 #define USART6_BASE U(0x44003000) 204 #define UART7_BASE U(0x40018000) 205 #define UART8_BASE U(0x40019000) 206 #define STM32MP_UART_BAUDRATE U(115200) 207 208 /* For UART crash console */ 209 #define STM32MP_DEBUG_USART_BASE UART4_BASE 210 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */ 211 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 212 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE 213 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR 214 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN 215 #define DEBUG_UART_TX_GPIO_PORT 11 216 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 217 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR 218 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI 219 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR 220 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN 221 222 /******************************************************************************* 223 * STM32MP1 TZC (TZ400) 224 ******************************************************************************/ 225 #define STM32MP1_TZC_BASE U(0x5C006000) 226 227 #define STM32MP1_TZC_A7_ID U(0) 228 #define STM32MP1_TZC_M4_ID U(1) 229 #define STM32MP1_TZC_LCD_ID U(3) 230 #define STM32MP1_TZC_GPU_ID U(4) 231 #define STM32MP1_TZC_MDMA_ID U(5) 232 #define STM32MP1_TZC_DMA_ID U(6) 233 #define STM32MP1_TZC_USB_HOST_ID U(7) 234 #define STM32MP1_TZC_USB_OTG_ID U(8) 235 #define STM32MP1_TZC_SDMMC_ID U(9) 236 #define STM32MP1_TZC_ETH_ID U(10) 237 #define STM32MP1_TZC_DAP_ID U(15) 238 239 #define STM32MP1_FILTER_BIT_ALL U(3) 240 241 /******************************************************************************* 242 * STM32MP1 SDMMC 243 ******************************************************************************/ 244 #define STM32MP_SDMMC1_BASE U(0x58005000) 245 #define STM32MP_SDMMC2_BASE U(0x58007000) 246 #define STM32MP_SDMMC3_BASE U(0x48004000) 247 248 #define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/ 249 #define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/ 250 #define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/ 251 #define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/ 252 #define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/ 253 254 /******************************************************************************* 255 * STM32MP1 BSEC / OTP 256 ******************************************************************************/ 257 #define STM32MP1_OTP_MAX_ID 0x5FU 258 #define STM32MP1_UPPER_OTP_START 0x20U 259 260 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) 261 262 /* OTP offsets */ 263 #define DATA0_OTP U(0) 264 #define PART_NUMBER_OTP U(1) 265 #define PACKAGE_OTP U(16) 266 #define HW2_OTP U(18) 267 268 /* OTP mask */ 269 /* DATA0 */ 270 #define DATA0_OTP_SECURED BIT(6) 271 272 /* PART NUMBER */ 273 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0) 274 #define PART_NUMBER_OTP_PART_SHIFT 0 275 276 /* PACKAGE */ 277 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27) 278 #define PACKAGE_OTP_PKG_SHIFT 27 279 280 /* IWDG OTP */ 281 #define HW2_OTP_IWDG_HW_POS U(3) 282 #define HW2_OTP_IWDG_FZ_STOP_POS U(5) 283 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7) 284 285 /* HW2 OTP */ 286 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13) 287 288 /******************************************************************************* 289 * STM32MP1 TAMP 290 ******************************************************************************/ 291 #define TAMP_BASE U(0x5C00A000) 292 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 293 294 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 295 static inline uint32_t tamp_bkpr(uint32_t idx) 296 { 297 return TAMP_BKP_REGISTER_BASE + (idx << 2); 298 } 299 #endif 300 301 /******************************************************************************* 302 * STM32MP1 DDRCTRL 303 ******************************************************************************/ 304 #define DDRCTRL_BASE U(0x5A003000) 305 306 /******************************************************************************* 307 * STM32MP1 DDRPHYC 308 ******************************************************************************/ 309 #define DDRPHYC_BASE U(0x5A004000) 310 311 /******************************************************************************* 312 * STM32MP1 IWDG 313 ******************************************************************************/ 314 #define IWDG_MAX_INSTANCE U(2) 315 #define IWDG1_INST U(0) 316 #define IWDG2_INST U(1) 317 318 #define IWDG1_BASE U(0x5C003000) 319 #define IWDG2_BASE U(0x5A002000) 320 321 /******************************************************************************* 322 * STM32MP1 I2C4 323 ******************************************************************************/ 324 #define I2C4_BASE U(0x5C002000) 325 326 /******************************************************************************* 327 * STM32MP1 DBGMCU 328 ******************************************************************************/ 329 #define DBGMCU_BASE U(0x50081000) 330 331 /******************************************************************************* 332 * Device Tree defines 333 ******************************************************************************/ 334 #define DT_BSEC_COMPAT "st,stm32mp15-bsec" 335 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" 336 #define DT_PWR_COMPAT "st,stm32mp1-pwr" 337 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 338 #define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" 339 340 #endif /* STM32MP1_DEF_H */ 341