Merge "fix(qemu_sbsa): align FIP base to BL1 size" into integration

fix(qemu_sbsa): align FIP base to BL1 size

RME patch series shown that we can build larger BL1 than we can run:

NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOT

fix(qemu_sbsa): align FIP base to BL1 size

RME patch series shown that we can build larger BL1 than we can run:

NOTICE: Booting Trusted Firmware
NOTICE: BL1: v2.9(debug):v2.9.0-736-g08548888a
NOTICE: BL1: Built : 12:10:39, Sep 18 2023
INFO: BL1: RAM 0x3ffee000 - 0x3fffb000
INFO: BL1: Loading BL2
WARNING: Firmware Image Package header check failed.

RME pushed debug build BL1 over 0x8000 in size.
This exposed an error where FIP_BASE (supposed to be at BL1_SIZE offset
from start of flash) was actually 0x8000 and not 0x12000.
Make sure we have space for BL1 by deriving FIP_BASE from it.

Note: this is a breaking change for edk2 FD image generation, which had
similarly hardcoded a 0x8000 offset. These images must be updated in
lock-step.

Change-Id: I8a1a85e82319945a4412c424467d818d5b6e4ecd
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu): add "neoverse-n2" cpu support

Add support to qemu "neoverse-n2" cpu for "qemu" platform.
This one has 2^48 address space so will be used by both systems.

Signed-off-by: Marcin Juszkiewi

feat(qemu): add "neoverse-n2" cpu support

Add support to qemu "neoverse-n2" cpu for "qemu" platform.
This one has 2^48 address space so will be used by both systems.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I9f0fa23a4934d9464379495225e08adc121325b4

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Merge "feat(qemu): add A55 cpu support for virt" into integration

Merge "feat(qemu): add "cortex-a710" cpu support" into integration

feat(qemu): add A55 cpu support for virt

Add support to "cortex-a55" cpu for "qemu" ('virt') platform.

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Change-Id: I2693892be735eda91494b76732

feat(qemu): add A55 cpu support for virt

Add support to "cortex-a55" cpu for "qemu" ('virt') platform.

Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
Change-Id: I2693892be735eda91494b767322935ddb63c9f48

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feat(qemu): add "cortex-a710" cpu support

Add support to qemu "cortex-a710" cpu for "qemu" platform.

CPU is supported by qemu/virt only as qemu/sbsa-ref memory starts at
2^40 which is limit for Cor

feat(qemu): add "cortex-a710" cpu support

Add support to qemu "cortex-a710" cpu for "qemu" platform.

CPU is supported by qemu/virt only as qemu/sbsa-ref memory starts at
2^40 which is limit for Cortex-A710.

Switched 'qemu' platform to be built as armv8.5 to cover features of
new cpu core.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I035790eac41b2caf7f13167e53f48c16f0827754

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chore: remove MULTI_CONSOLE_API references

MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
reference

chore: remove MULTI_CONSOLE_API references

MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
references in platform.mk files and also in one rst which is not valid
anymore.

Change-Id: I45f8e7db0a14ce63de62509100d8159b7aca2657
Signed-off-by: Michal Simek <michal.simek@amd.com>

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feat(qemu): add dummy plat_mboot_measure_key() BL1 function

Adds a dummy implementation of the plat_mboot_measure_key() function in
BL1 for QEMU platform.

Signed-off-by: Jens Wiklander <jens.wiklan

feat(qemu): add dummy plat_mboot_measure_key() BL1 function

Adds a dummy implementation of the plat_mboot_measure_key() function in
BL1 for QEMU platform.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I5923aad962a5e34d657cf49c177e68ed2ea93291

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refactor(qemu): handle pointer authentication

Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.

Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszki

refactor(qemu): handle pointer authentication

Pointer authentication requires CTX_INCLUDE_PAUTH_REGS to be defined.

Change-Id: I4ca95d6d9e619e7a7296a2c3ecb799683bf70575
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: M

refactor(qemu): move options to start of file

There are some variables to enable/disable options. Let keep them at top
of file.

Change-Id: I108dd814557b6c713aba0d73a52148c766079c8b
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): keep AArch64 cpu flags in one section

There is no need to have two "if" checks for same thing one after
another.

FGT, RNG, SVE, SME are aarch64 only flags.

Change-Id: I6e5850211c85

refactor(qemu): keep AArch64 cpu flags in one section

There is no need to have two "if" checks for same thing one after
another.

FGT, RNG, SVE, SME are aarch64 only flags.

Change-Id: I6e5850211c859dc7a4ccf6bc8dc6a8d600ffe692
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14

refactor(qemu): handle SPM_MM builds

SPM_MM is not compatible with ENABLE_SVE_FOR_NS and breaks build early:

> Including SPM Management Mode (MM) makefile
> services/std_svc/spm/spm_mm/spm_mm.mk:14: *** "Error: SPM_MM is not compatible with ENABLE_SVE_FOR_NS". Stop.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: Iabe181647fce00a432ae11dc4599b71619364c24

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refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linar

refactor(qemu): handle AArch64 flags

Handle coherency in one place for AArch64 mode.

Change-Id: Id3678a8f478e5ef731c81c0df30059000e380758
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): common cpu features enablement

Enable SVE, SME, RNG, FGT in one place.

qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG

Signed-off-by: Marcin Juszkiewicz <ma

refactor(qemu): common cpu features enablement

Enable SVE, SME, RNG, FGT in one place.

qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I2e8f971ef3e42d9ebe9f20641b288cc8c40f806a

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refactor(qemu): common BL31 sources

Move BL31 source list into common file.

Change-Id: Iaa27cfd8f87b691728379c87a6ff6331e87951e1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

refactor(qemu): common BL1/2 sources

Move BL1 and BL2 source list into common file.

Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro

refactor(qemu): common BL1/2 sources

Move BL1 and BL2 source list into common file.

Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move CPU definitions into one place

Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not

refactor(qemu): move CPU definitions into one place

Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not matter.

Change-Id: I5b8f7d18dc903e86e0cc7babbc2fb3f26a1bfdfa
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): move FDT stuff into one place

Move libfdt includes into common file and use definitions from them.

Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkie

refactor(qemu): move FDT stuff into one place

Move libfdt includes into common file and use definitions from them.

Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu): add dummy plat_mboot_measure_key() function

Adds a dummy implementation of the plat_mboot_measure_key() function for
QEMU platform.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.

feat(qemu): add dummy plat_mboot_measure_key() function

Adds a dummy implementation of the plat_mboot_measure_key() function for
QEMU platform.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I64c1c751348c04cd359c075fc15a0d180ff55918

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Merge "feat(qemu): add "neoverse-v1" cpu support" into integration

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu" ('virt') platform.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I4821115b5

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu" ('virt') platform.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I4821115b54ca596fe27cb9d74a95429cd3cb21d9

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feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Change-Id: Id710e2b960e7938d2dbe7a88d9e158a7009fc3d1
Signed-off-by: Marcin Jus

feat(qemu): add "neoverse-v1" cpu support

Add support to qemu "neoverse-v1" cpu for "qemu_sbsa" ('sbsa-ref')
platform.

Change-Id: Id710e2b960e7938d2dbe7a88d9e158a7009fc3d1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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feat(qemu_sbsa): handle GIC ITS address

Read data from DeviceTree provided by QEMU, provide via SMC
to the next firmware level.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Cha

feat(qemu_sbsa): handle GIC ITS address

Read data from DeviceTree provided by QEMU, provide via SMC
to the next firmware level.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I95c5f00ab2cca3b5fda122dcc8d7704a7a82059b

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refactor(build): merge march32/64 directives

Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives

refactor(build): merge march32/64 directives

Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.

Merge this two separate directives to a common one as march-directive.

Change-Id: I220d2b782eb3b54e13ffd5b6a581d0e6da68756a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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