feat(qemu-sbsa): relocate DT after the RMM when RME is enabled

When RME is enabled, (1) the RMM is installed at the base of system RAM,
(2) the base of the system RAM is shifted upward, after the RM

feat(qemu-sbsa): relocate DT after the RMM when RME is enabled

When RME is enabled, (1) the RMM is installed at the base of system RAM,
(2) the base of the system RAM is shifted upward, after the RMM and (3)
the device tree is relocated to the new system RAM base.

This patch relocates the device tree to the new system RAM base before
the RMM is installed in RAM. From there, other accesses to the device
tree are using the new location.

Change-Id: I0cb4e060ca33a11becd78fe48fab4dc76f0b484b
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful

There is no relation between the name of function sip_svc_init() and
what it does. As such rename it to something mo

refactor(qemu-sbsa): rename function sip_svc_init() to something more meaningful

There is no relation between the name of function sip_svc_init() and
what it does. As such rename it to something more appropriate and move
it to a header that make sense.

No change in functionality.

Change-Id: I7bd78b1fe70e2930c395ef0a097bfad3b1e55d3a
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu): make L0GPT size configurable

Add a new parameter to make the size of the L0GPT configurable based on
the amount of memory available on a platform. That way platform with a
wider phys

refactor(qemu): make L0GPT size configurable

Add a new parameter to make the size of the L0GPT configurable based on
the amount of memory available on a platform. That way platform with a
wider physical address range can be supported.

No change in functionality.

Change-Id: I5b7b4968636d61929ad6ebdc05c389291cf510b1
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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refactor(qemu): move GPT setup to BL31

Some platforms such as QEMU-SBSA access the device tree located at the
bottom of the non-secure RAM from BL31. When GPT checks are enabled at
BL2, that access

refactor(qemu): move GPT setup to BL31

Some platforms such as QEMU-SBSA access the device tree located at the
bottom of the non-secure RAM from BL31. When GPT checks are enabled at
BL2, that access generates a GPT check fault because the device tree
area is configure as non-secure RAM and the access is made from secure
EL3.

We could change the device tree memory area configuration in a way that
it is accessible from BL31, but that would require another configuration
of the GPT before going to BL33.

Since BL2 and BL31 are both running at EL3, a better solution is simply
move the GPT configuration and enabling to BL31, after the device tree
has been probed.

No change in functionality.

Change-Id: Ifa01c50164268b993d563c32e4e42140259c44e2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
[Added changelog description]
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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fix(qemu-sbsa): fix compilation error when accessing DT functions

When building SBSA, using DT functions from fdt_wrappers.c produces a
linker error. Adding:

BL2_SOURCES += ${FDT_WRAPPERS_SOURCES}

fix(qemu-sbsa): fix compilation error when accessing DT functions

When building SBSA, using DT functions from fdt_wrappers.c produces a
linker error. Adding:

BL2_SOURCES += ${FDT_WRAPPERS_SOURCES}

fixes the problem. Since the same inclusion would be present in both
qemu/platform.mk and qemu_sbsa/platform.mk, do the changes in
qemu/common/common.mk.

Change-Id: I775b06c1741f6618813c5e1d2c64cdc1888d8519
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>

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fix(qemu): fix EL3-SPMC data store alignment

With PLAT=qemu, the EL3-SPMC data store is provided as an array of
uint8_t and implicitly with a 1 byte alignment. But the way the data
store is used it

fix(qemu): fix EL3-SPMC data store alignment

With PLAT=qemu, the EL3-SPMC data store is provided as an array of
uint8_t and implicitly with a 1 byte alignment. But the way the data
store is used it must have a larger alignment, so change to double-word
alignment for maximum compatibility.

Change-Id: I4e9b901889078fee4b87f8333257bdc076386572
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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fix(qemu): fix build error with spmd

Currently when building with PLAT=qemu SPD=spmd SPMC_AT_EL3=1
SPMD_SPM_AT_SEL2=0, there is a build error since
plat_spmd_handle_group0_interrupt() is called irre

fix(qemu): fix build error with spmd

Currently when building with PLAT=qemu SPD=spmd SPMC_AT_EL3=1
SPMD_SPM_AT_SEL2=0, there is a build error since
plat_spmd_handle_group0_interrupt() is called irrespective of
SPMC_AT_EL3. Fix this by making plat_spmd_handle_group0_interrupt()
available if SPD_spmd is defined only.

Change-Id: If5f650d2bd3675cbb4b509e9e3743d3865d7c812
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Merge "fix(qemu): update rmmd_attest_get_platform_token()" into integration

fix(qemu): update rmmd_attest_get_platform_token()

Update the parameters to rmmd_attest_get_platform_token(), which can now
handle platform tokens larger than 4kB. Since the QEMU sample token is
sma

fix(qemu): update rmmd_attest_get_platform_token()

Update the parameters to rmmd_attest_get_platform_token(), which can now
handle platform tokens larger than 4kB. Since the QEMU sample token is
smaller than 4kB, our implementation remains the same. Take the
opportunity to clean up the function slightly.

Change-Id: Id5a1d576968ebd160d2b79c1f38392d4ecc89421
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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refactor(qemu): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-c

refactor(qemu): use the example CCA platform token from iat-verifier

In [1] and [2], the example CCA platform token has been updated to be
aligned with the new profile(s) defined in draft-ffm-rats-cca-token-00.

This change replaces the static CCA platform token in QEMU.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/30812
[2] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/31036

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9153df1e6c1be81e669d5495dbe8d1a52e86cdff

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Merge "feat(handoff): fix register convention r1/x1 value on transfer list" into integration

feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was chang

feat(handoff): fix register convention r1/x1 value on transfer list

According to recently firmware handsoff spec [1]'s "Register usage at handoff
boundary", Transfer List's signature value was changed from 0x40_b10b
(3 bytes) to 4a0f_b10b (4 bytes).

As updating of TL's signature, register value of x1/r1 should be:

In aarch32's r1 value should be
R1[23:0]: set to the TL signature (4a0f_b10b -> masked range value: 0f_b10b)
R1[31:24]: version of the register convention == 1
and
In aarch64's x1 value should be
X1[31:0]: set to the TL signature (4a0f_b10b)
X1[39:32]: version of the register convention == 1
X1[63:40]: MBZ
(See the [2] and [3]).

Therefore, it requires to separate mask and shift value for register
convention version field when sets each r1/x1.

This patch fix two problems:
1. breaking X1 value with updated specification in aarch64
- change of length of signature field.

2. previous error value set in R1 in arm32.
- length of signature should be 24, but it uses 32bit signature.

This change is breaking change. It requires some patch for other
softwares (u-boot[4], optee[5]).

Link: https://github.com/FirmwareHandoff/firmware_handoff [1]
Link: https://github.com/FirmwareHandoff/firmware_handoff/issues/32 [2]
Link: https://github.com/FirmwareHandoff/firmware_handoff/commit/5aa7aa1d3a1db75213e458d392b751f0707de027 [3]
Link: https://lists.denx.de/pipermail/u-boot/2024-July/558628.html [4]
Link: https://github.com/OP-TEE/optee_os/pull/6933 [5]
Signed-off-by: Levi Yun <yeoreum.yun@arm.com>
Change-Id: Ie417e054a7a4c192024a2679419e99efeded1705

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Merge "fix(qemu): remove validate_ns_entrypoint" into integration

fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 G

fix(qemu): allocate space for GPT bitlock

Since commit ec0088bbab93 ("feat(gpt): add support for large GPT
mappings"), the platform needs to reserve space for the bitlock,
immediately after the L0 GPT table. Add two pages to the L0 GPT reserve.
This could be optimized later by moving the bitlock somewhere else,
because it really only needs (1 << PPS.T) / (512M * 8) = 256 bytes for
the QEMU virt platform.

Fix two more comments in qemu_pas_def.h since we're here.

Change-Id: I2b0b8de38f4b5058735ed16f1cdc50e6b2d52ad9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This

fix(qemu): remove validate_ns_entrypoint

QEMU has dynamic memory configuration based on -m parameter. The
hard-coded values in TF-A are not accurate when starting the model with
this parameter. This is not a problem when loading boot images as the
lower addresses are the same. However, it can be a problem when starting
up the secondary CPUs with a rather high non-secure entry point. So fix
this by removing the plat_psci_ops_t validate_ns_entrypoint assignment
to allow any non-secure entry point.

Change-Id: I95e92b71e0f4fa5f94444ea0cd2cb42e56faa472
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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refactor(qemu): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software compon

refactor(qemu): use the example CCA platform token from iat-verifier

In [1], the example CCA platform token has been updated to fix a small
problem with the description of one of the software components, and to
provide a more realistic breakdown of the expected components in the CCA
TCB.

This change replaces the static CCA platform token in QEMU.

[1] https://review.trustedfirmware.org/c/TF-M/tf-m-tools/+/28493

Change-Id: I8ce49e6ecf83c426dee9024e782a8da457316959
Signed-off-by: Thomas Fossati <thomas.fossati@linaro.org>

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refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all th

refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all the features:

-> is_feat_xx_present(): Does Hardware implement the feature.
-> uniformity in naming the function across multiple features.
-> improved readability

The is_feat_xx_present() is implemented to check if the hardware
implements the feature and does not take into account the
ENABLE_FEAT_XXX flag enabled/disabled in software.

- CREATE_FEATURE_PRESENT(name, idreg, shift, mask, idval)
The wrapper macro reduces the function to a single line and
creates the is_feat_xx_present function that checks the
id register based on the shift and mask values and compares
this against a determined idvalue.

Change-Id: I7b91d2c9c6fbe55f94c693aa1b2c50be54fb9ecc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fv

Merge changes from topic "rss_rse_rename" into integration

* changes:
refactor(changelog): change all occurrences of RSS to RSE
refactor(qemu): change all occurrences of RSS to RSE
refactor(fvp): change all occurrences of RSS to RSE
refactor(fiptool): change all occurrences of RSS to RSE
refactor(psa): change all occurrences of RSS to RSE
refactor(fvp): remove leftovers from rss measured boot support
refactor(tc): change all occurrences of RSS to RSE
docs: change all occurrences of RSS to RSE
refactor(measured-boot): change all occurrences of RSS to RSE
refactor(rse): change all occurrences of RSS to RSE
refactor(psa): rename all 'rss' files to 'rse'
refactor(tc): rename all 'rss' files to 'rse'
docs: rename all 'rss' files to 'rse'
refactor(measured-boot): rename all 'rss' files to 'rse'
refactor(rss): rename all 'rss' files to 'rse'

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feat(qemu): update to manifest v0.3

Update the RMM manifest to v0.3: pass the console information to RMM.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Change-Id: I55093cd0c12f9c6

feat(qemu): update to manifest v0.3

Update the RMM manifest to v0.3: pass the console information to RMM.

Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Change-Id: I55093cd0c12f9c6a7569d7e524f7d301acbb2a45

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Merge "feat(qemu): allow ARM_ARCH_MAJOR/MINOR override" into integration

Merge "feat(qemu): enable FEAT_ECV when present" into integration

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPD

refactor(qemu): do not hardcode counter frequency

From QEMU change:

> In previous versions of the Arm architecture, the frequency of the
> generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value,
> and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns.
> In Armv8.6, the architecture standardized this frequency to 1GHz.

This change stops TF-A from hardcoding 62.5MHz frequency. Instead value
stored in CNTFRQ_EL0 would be used. As a result we get 62.5MHz on older
cores and 1GHz on newer ones.

Change-Id: I7d414ce6d3708e598bbb5a6f79eb2d4ec8e15ac4
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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refactor(qemu): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-I

refactor(qemu): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I2c6840f6f3f2f8f64595a0e0aa6e12084a37ce6e

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feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the

feat(qemu): allow ARM_ARCH_MAJOR/MINOR override

An upcoming change to the RME support code will use atomic instructions
introduced in Armv8.1 in order to implement bitlocks. In order to do
this, the code needs to be built with appropriate -march compiler flag
(otherwise the assembler complains about invalid instructions). One way
to do this is specifying ARM_ARCH_MAJOR/MINOR version greater than 8.0,
which is what the main Makefile does when ENABLE_RME is set.

Allow the main Makefile to override the ARM_ARCH_MAJOR/MINOR variables
on the QEMU platform, so that it can also build the bitlock functions.

This only affects firmware built with ENABLE_RME, which is an
experimental feature both in TF-A and QEMU. The QEMU platform code
doesn't support booting an ENABLE_RME firmware on non-RME CPUs at the
moment.

As a result of this change, when ENABLE_RME is set,
make_helpers/arch_features.mk sets ENABLE_TRF_FOR_NS to 1, which needs
to be overridden by the QEMU Makefile.

Change-Id: I695fc98b21d07f6c84003d9e36a57cad2a3c806e
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the fe

feat(qemu): enable FEAT_ECV when present

QEMU supports FEAT_ECV since commit 2808d3b38a52 ("target/arm: Implement
FEAT_ECV CNTPOFF_EL2 handling"), in the v9.0.0 release. Enable
auto-detecting the feature on the QEMU platforms, in order to set
SCR.ECVEN. Without this, EL2 gets undefined instruction exceptions when
trying to access the new CNTPOFF register.

Change-Id: I555a5f9a9a84fd23e64ca85219ed1599204c6bb2
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>

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