Tegra: spe: do not flush console in console_putc

SPE no longer requires the flush bit to be set to start transmitting
characters over the physical uart. Therefore, the flush bit is no
longer require

Tegra: spe: do not flush console in console_putc

SPE no longer requires the flush bit to be set to start transmitting
characters over the physical uart. Therefore, the flush bit is no
longer required when calling console_core_putc. However, flushing the
console still requires the flush bit.

This patch removes the flush bit from the mailbox messages in
console_core_putc to improve ACK latency.

Original change by: Mustafa Bilgen <mbilgen@nvidia.com>

Change-Id: I5b7d1f3ea69ea2ce308566dbaae222b04e4c373d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: verify platform compatibility

This patch verifies that the binary image is compatible with
chip ID of the platform.

Change-Id: I28db221b4442aa8827a092faadf32f110d7c5cb4
Signed-off-by: kalyan

Tegra: verify platform compatibility

This patch verifies that the binary image is compatible with
chip ID of the platform.

Change-Id: I28db221b4442aa8827a092faadf32f110d7c5cb4
Signed-off-by: kalyanic <kalyanic@nvidia.com>

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Revert "libc/memset: Implement function in assembler"

This reverts commit e7d344de01ad11b856233634717aafe9312697e4.
This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware

Revert "libc/memset: Implement function in assembler"

This reverts commit e7d344de01ad11b856233634717aafe9312697e4.
This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5313 due to a timing issue with the merge. The merge occurred at the same time as the additional comments and thusly were were not seen until the merge was done. This reverts the change and additional patches from Alexei will follow to address the concerns expressed in the orignal patch.

Change-Id: Iae5f6403c93ac13ceeda29463883fcd4c437f2b7

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libc/memset: Implement function in assembler

Trace analysis of FVP_Base_AEMv8A model running in
Aarch32 mode with the build options listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATI

libc/memset: Implement function in assembler

Trace analysis of FVP_Base_AEMv8A model running in
Aarch32 mode with the build options listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
shows that when auth_signature() gets called
71.84% of CPU execution time is spent in memset() function
written in C using single byte write operations,
see lib\libc\memset.c.
This patch replaces C memset() implementation with assembler
version giving the following results:
- for Aarch32 in auth_signature() call memset() CPU time
reduced to 24.84%.
- Number of CPU instructions executed during TF-A
boot stage before start of BL33 in RELEASE builds:
----------------------------------------------
| Arch | C | assembler | % |
----------------------------------------------
| Aarch32 | 2073275460 | 1487400003 | -28.25 |
| Aarch64 | 2056807158 | 1244898303 | -39.47 |
----------------------------------------------
The patch also replaces memset.c with aarch64/memset.S
in plat\nvidia\tegra\platform.mk.

Change-Id: Ifbf085a2f577a25491e2d28446ee95a4ac891597
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Tegra: platform: add function to check t194 chip

This patch adds tegra_chipid_is_t194() function to check if it is a
Tegra 194 chip.

Change-Id: I6da6d3a2c9676b748931e42fde1b174cbcb4fd40
Signed-off-

Tegra: platform: add function to check t194 chip

This patch adds tegra_chipid_is_t194() function to check if it is a
Tegra 194 chip.

Change-Id: I6da6d3a2c9676b748931e42fde1b174cbcb4fd40
Signed-off-by: David Pu <dpu@nvidia.com>

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Tegra: common: make plat_psci_ops routines static

This patch makes Tegra platform psci ops routines to static. These
routines are called by PSCI framework and no external linkage is
necessary. This

Tegra: common: make plat_psci_ops routines static

This patch makes Tegra platform psci ops routines to static. These
routines are called by PSCI framework and no external linkage is
necessary. This patch also fixes MISRA C-2012 Rule 8.6 violations.

Change-Id: Idd2381809f76dc0fd578c1c92c0f8eea124f2e88
Signed-off-by: David Pu <dpu@nvidia.com>

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Tegra: memctrl: remove unused TZRAM setup function

This patch removes the unused TZRAM setup function from the memory
controller driver.

Change-Id: Ic16f21fb84c47df71be6ab3e1e286640daa39291
Signed-

Tegra: memctrl: remove unused TZRAM setup function

This patch removes the unused TZRAM setup function from the memory
controller driver.

Change-Id: Ic16f21fb84c47df71be6ab3e1e286640daa39291
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: reorganize drivers and lib folders

This patch moves the 'drivers' and the 'lib' folders out of the
'common' folder. This way the 'common' folder shall contain only
the platform support requir

Tegra: reorganize drivers and lib folders

This patch moves the 'drivers' and the 'lib' folders out of the
'common' folder. This way the 'common' folder shall contain only
the platform support required for all Tegra platforms.

Change-Id: I2f238572d0a078d60c6b458a559538dc8a4d1856
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Use abspath to dereference $BUILD_BASE

If the user tries to change BUILD_BASE to put the build products outside
the build tree the compile will fail due to hard coded assumptions that
$BUILD_BASE is

Use abspath to dereference $BUILD_BASE

If the user tries to change BUILD_BASE to put the build products outside
the build tree the compile will fail due to hard coded assumptions that
$BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE))
to rationalize to an absolute path every time and remove the relative
path assumptions.

This patch also adds documentation that BUILD_BASE can be specified by
the user.

Signed-off-by: Grant Likely <grant.likely@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8

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plat/nvidia: tegra: Enable SMCCC_ARCH_SOC_ID feature

Enabled 'SMCCC_ARCH_SOC_ID' feature for Nvidia Tegra platforms.

Change-Id: If17415f42304c6518aeead8dfe5909c378aaa777
Signed-off-by: Manish V Bad

plat/nvidia: tegra: Enable SMCCC_ARCH_SOC_ID feature

Enabled 'SMCCC_ARCH_SOC_ID' feature for Nvidia Tegra platforms.

Change-Id: If17415f42304c6518aeead8dfe5909c378aaa777
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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TF-A GICv2 driver: Introduce makefile

This patch moves all GICv2 driver files into new added
'gicv2.mk' makefile for the benefit of the generic driver
which can evolve in the future without affectin

TF-A GICv2 driver: Introduce makefile

This patch moves all GICv2 driver files into new added
'gicv2.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.

NOTE: Usage of 'drivers/arm/gic/common/gic_common.c' file
is now deprecated and platforms with GICv2 driver need to
be modified to include 'drivers/arm/gic/v2/gicv2.mk' in
their makefiles.

Change-Id: Ib10e71bdda0e5c7e80a049ddce2de1dd839602d1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge changes from topic "tegra-memctrlv2-vpr-resize-bugfix" into integration

* changes:
Tegra: sanity check NS address and size before use
Tegra: memctrl_v2: fixup sequence to resize video memo

Merge changes from topic "tegra-memctrlv2-vpr-resize-bugfix" into integration

* changes:
Tegra: sanity check NS address and size before use
Tegra: memctrl_v2: fixup sequence to resize video memory

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Tegra: sanity check NS address and size before use

This patch updates the 'bl31_check_ns_address()' helper function to
check that the memory address and size passed by the NS world are not
zero.

Th

Tegra: sanity check NS address and size before use

This patch updates the 'bl31_check_ns_address()' helper function to
check that the memory address and size passed by the NS world are not
zero.

The helper fucntion also returns the error code as soon as it detects
inconsistencies, to avoid multiple error paths from kicking in for the
same input parameters.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Change-Id: I46264f913954614bedcbde12e47ea0c70cd19be0

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Tegra: introduce support for GICv3

This patch provides the platform level support to enable GICv3
drivers on future Tegra platforms.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I9

Tegra: introduce support for GICv3

This patch provides the platform level support to enable GICv3
drivers on future Tegra platforms.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I966a4502b2a4a7bd1ce66da843997c9ed605c59f

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Tegra: memctrl_v2: fixup sequence to resize video memory

The previous sequence used by the driver to program the new memory
aperture settings and clear the non-overlapping memory was faulty.
The seq

Tegra: memctrl_v2: fixup sequence to resize video memory

The previous sequence used by the driver to program the new memory
aperture settings and clear the non-overlapping memory was faulty.
The sequence locked the non-overlapping regions twice, leading to
faults when trying to clear it.

This patch modifies the sequence to follow these steps:

* move the previous memory region to a new firewall register
* program the new memory aperture settings
* clean the non-overlapping memory

This patch also maps the non-overlapping memory as Device memory to
follow guidance from the arch. team.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I7cf6e05b2dd372103dc7229e37b1b3fc269a57ae

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Tegra194: ras: verbose prints for SErrors

This patch provides verbose prints for RAS SErrors handled by the
firmware, for improved debugging.

Change-Id: Iaad8d183054d884f606dc4621da2cc6b2375bcf9
Si

Tegra194: ras: verbose prints for SErrors

This patch provides verbose prints for RAS SErrors handled by the
firmware, for improved debugging.

Change-Id: Iaad8d183054d884f606dc4621da2cc6b2375bcf9
Signed-off-by: David Pu <dpu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: SiP: clear RAS corrected error records

This patch introduces a function ID to clear all the RAS error
records for corrected errors.

Per latest requirement, ARM RAS corrected errors will b

Tegra194: SiP: clear RAS corrected error records

This patch introduces a function ID to clear all the RAS error
records for corrected errors.

Per latest requirement, ARM RAS corrected errors will be reported to
lower ELs via interrupts and cleared via SMC. This patch provides
required function to clear RAS error status.

This patch also sets up all required RAS Corrected errors in order to
route RAS corrected errors to lower ELs.

Change-Id: I554ba1d0797b736835aa27824782703682c91e51
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Signed-off-by: David Pu <dpu@nvidia.com>

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Tegra194: add RAS exception handling

This patch adds all Tegra194 RAS nodes definitions and support to
handle all uncorrectable RAS errors.

Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9
Sign

Tegra194: add RAS exception handling

This patch adds all Tegra194 RAS nodes definitions and support to
handle all uncorrectable RAS errors.

Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9
Signed-off-by: David Pu <dpu@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Merge "Tegra: enable SDEI handling" into integration

Merge "Tegra194: validate C6 power state type" into integration

Merge "Tegra194: remove support for CPU suspend power down state" into integration

Tegra: enable SDEI handling

This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.

* SGI 8 as the source IRQ
* Special Private Event 0
* Three private,

Tegra: enable SDEI handling

This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.

* SGI 8 as the source IRQ
* Special Private Event 0
* Three private, dynamic events
* Three shared, dynamic events
* Twelve general purpose explicit events

Verified using TFTF SDEI test suite.

******************************* Summary *******************************
Test suite 'SDEI' Passed
=================================
Tests Skipped : 0
Tests Passed : 5
Tests Failed : 0
Tests Crashed : 0
Total tests : 5
=================================

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390

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Tegra: enable stack protection

This patch sets ENABLE_STACK_PROTECTOR=strong and implements
the platform support to generate a stack protection canary value.

Signed-off-by: Varun Wadekar <vwadekar@

Tegra: enable stack protection

This patch sets ENABLE_STACK_PROTECTOR=strong and implements
the platform support to generate a stack protection canary value.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ia8afe464b5645917b1c77d49305d19c7cd01866a

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Tegra: introduce support for SMCCC_ARCH_SOC_ID

This patch returns the SOC version and revision values from
the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers.

Verified using TFTF SMCCC

Tegra: introduce support for SMCCC_ARCH_SOC_ID

This patch returns the SOC version and revision values from
the 'plat_get_soc_version' and 'plat_get_soc_revision' handlers.

Verified using TFTF SMCCC_ARCH_SOC_ID test.

<snip>
> Executing 'SMCCC_ARCH_SOC_ID test'
TEST COMPLETE Passed
SOC Rev = 0x102
SOC Ver = 0x36b0019
<snip>

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibd7101619143b74f6f6660732daeac1a8bca3e44

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Tegra194: validate C6 power state type

This patch validates that PSTATE_STANDBY is set as the C6 power state type.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I26a4a61bcb4ee0d1846

Tegra194: validate C6 power state type

This patch validates that PSTATE_STANDBY is set as the C6 power state type.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I26a4a61bcb4ee0d1846ab61c007eeba3c180e5aa

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