Tegra: memctrl_v2: platform handler for TZDRAM settings

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers

Tegra: memctrl_v2: platform handler for TZDRAM settings

The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.

Change-Id: Ifaa2e0eac20b50f77ec734256544c36dd511bd63
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: secondary: fix MISRA violations for Rules 8.6, 11.1

This patch fixes the following MISRA violations:

Rule 8.6: Externally-linked object or function has "no" definition(s).
Rule 11.1: A ca

Tegra186: secondary: fix MISRA violations for Rules 8.6, 11.1

This patch fixes the following MISRA violations:

Rule 8.6: Externally-linked object or function has "no" definition(s).
Rule 11.1: A cast shall not convert a pointer to a function to
any other type.

Change-Id: Ic1f6fc14c744e54ff782c6987dab9c9430410f5e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware

This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for cloc

Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware

This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/
disable requests, module resets among other things.

MRQ is short for Message ReQuest. This is the general purpose, multi channel
messaging protocol that is widely used to communicate with BPMP. This is further
divided into a common high level protocol and a peer-specific low level protocol.
The higher level protocol specifies the peer identification, channel definition
and allocation, message structure, message semantics and message dispatch process
whereas the lower level protocol defines actual message transfer implementation
details. Currently, BPMP supports two lower level protocols - Token Mail Operations
(TMO), IVC Mail Operations (IMO).

This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM
Communication) protocol which is a lockless, shared memory messaging queue management
protocol.

The IVC peer is expected to perform the following as part of establishing a connection
with BPMP.

1. Initialize the channels with tegra_ivc_init() or its equivalent.
2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that
BPMP is notified via the doorbell.
3. Poll until the channel connection is established [tegra_ivc_channel_notified() return
0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return
non zero.

The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In
future, more hardware blocks would be supported.

Change-Id: I52a4bd3a853de6c4fa410904b6614ff1c63df364
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: allow CPU accesses to TZRAM

This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.

Change-Id: I0898582f8bd6fd35360e

Tegra: memctrl_v2: allow CPU accesses to TZRAM

This patch enables CPU access configuration register to allow
accesses to the TZRAM aperture on chips after Tegra186.

Change-Id: I0898582f8bd6fd35360ecf8ca5cee21fe35f7aab
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH

This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exitin

Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH

This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exiting System Suspend.

Change-Id: Id76175c2a7d931227589468511365599e2908411
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra: memctrl_v2: platform handlers to program MSS

Introduce platform handlers to program the MSS settings.
This allows the current driver to scale to future chips.

Change-Id: I40a27648a1a3c73b1ce

Tegra: memctrl_v2: platform handlers to program MSS

Introduce platform handlers to program the MSS settings.
This allows the current driver to scale to future chips.

Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

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Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is re

Tegra: memctrl: clean MC INT status before exit to bootloader

This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is required as we observed that the MC's
arbitration bit is set before exiting the secure world.

Change-Id: Iacd01994d03b3b9cbd7b8a57fe7ab5b04e607a9f
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for t

Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO

This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for the warmboot firmware to restore.
SCRATCH54_HI is still being used for backward compatibility,
but would be removed eventually.

The scratch registers are populated as:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
* RSV54_1 = CFG1[12:0]

Change-Id: Idc20d165d8117488010fcc8dfd946f7ad475da58
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra210_B01: SC7: Select RNG mode based on ECID

If ECID is valid, we can use force instantiation
otherwise, we should use reseed for random data
generation for RNG operations in SE context save
DNI

Tegra210_B01: SC7: Select RNG mode based on ECID

If ECID is valid, we can use force instantiation
otherwise, we should use reseed for random data
generation for RNG operations in SE context save
DNI because we are not keeping software save
sequence in main.

Change-Id: I73d650e6f45db17b780834b8de4c10501e05c8f3
Signed-off-by: Samuel Payne <spayne@nvidia.com>

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Tegra210B01: SE/SE2 and PKA1 context save (SW)

This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save

Tegra210B01: SE/SE2 and PKA1 context save (SW)

This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save routine is intended to be invoked from
the ATF SC7 entry.

Change-Id: I9aa156d6e7e22a394bb10cb0c3b05fc303f08807
Signed-off-by: Marvin Hsu <marvinh@nvidia.com>

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Tegra: lib: library for profiling the cold boot path

The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) i

Tegra: lib: library for profiling the cold boot path

The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) is allocated and the base address is passed to
the EL3 firmware.

This patch adds a library to allow the platform code to store the
tag:timestamp pair to the shared memory. The tegra platform code
then uses the `record` method to add timestamps.

Original change by Akshay Sharan <asharan@nvidia.com>

Change-Id: Idbbef9c83ed84a508b04d85a6637775960dc94ba
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: fix defects flagged by MISRA Rule 10.3

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

Tegra: fix defects flagged by MISRA Rule 10.3

MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.

The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.

Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.

Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra210: se: enable entropy/SE clocks before system suspend

This patch enables clocks to the SE and Entropy block and gets them
out of reset, before starting the context save operation.

Change-Id:

Tegra210: se: enable entropy/SE clocks before system suspend

This patch enables clocks to the SE and Entropy block and gets them
out of reset, before starting the context save operation.

Change-Id: Ic196be8fb833dfd04c0e8d460c07058429999613
Signed-off-by: Samuel Payne <spayne@nvidia.com>

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Tegra: smmu: add a hook to get number of devices

This patch adds a hook to get the number of smmu devices and
removes the NUM_SMMU_DEVICES macro.

Change-Id: Ia8dba7e9304224976b5da688b9e4b5438f11cc4

Tegra: smmu: add a hook to get number of devices

This patch adds a hook to get the number of smmu devices and
removes the NUM_SMMU_DEVICES macro.

Change-Id: Ia8dba7e9304224976b5da688b9e4b5438f11cc41
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra: read-modify-write ACTLR_ELx registers

This patch changes direct writes to ACTLR_ELx registers to use
read-modify-write instead.

Change-Id: I6e0eaa6974583f3035cb3724088f3f1c849da229
Signed-of

Tegra: read-modify-write ACTLR_ELx registers

This patch changes direct writes to ACTLR_ELx registers to use
read-modify-write instead.

Change-Id: I6e0eaa6974583f3035cb3724088f3f1c849da229
Signed-off-by: Steven Kao <skao@nvidia.com>

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Tegra210: se: disable SMMU before suspending SE block

This patch disables SMMU hardware before suspending the SE
block, for the context save operation to complete. The NS
word will re-enable SMMU wh

Tegra210: se: disable SMMU before suspending SE block

This patch disables SMMU hardware before suspending the SE
block, for the context save operation to complete. The NS
word will re-enable SMMU when we exit System Suspend.

Change-Id: I4d5cd982ea6780db5c38b124550d847e3928c60d
Signed-off-by: Samuel Payne <spayne@nvidia.com>

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Tegra: common: drivers: fix MISRA defects

Main fixes:

Add suffix U for constant [Rule 10.1]

Match the operands type [Rule 10.4]

Use UL replace U for that constant define that need do "~"
operatio

Tegra: common: drivers: fix MISRA defects

Main fixes:

Add suffix U for constant [Rule 10.1]

Match the operands type [Rule 10.4]

Use UL replace U for that constant define that need do "~"
operation [Rule 12.4]

Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: Ia1e814ca3890eab7904be9c79030502408f30936
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra: pm: fix MISRA defects

Main fixes:

* Use int32_t replace int, use uint32_t replace unsign int
[Rule 4.6]
* Add function define to header file [Rule 8.4]
* Added curly braces ({}) around if

Tegra: pm: fix MISRA defects

Main fixes:

* Use int32_t replace int, use uint32_t replace unsign int
[Rule 4.6]
* Add function define to header file [Rule 8.4]
* Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
* Voided non c-library functions whose return types are not used
[Rule 17.7]

Change-Id: Ifa3ba4e75046697cfede885096bee9a30efe6519
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra: fix MISRA defects in tegra_bl31_setup.c

Main fixes:

Add parentheses to avoid implicit operator precedence [Rule 12.1]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

A

Tegra: fix MISRA defects in tegra_bl31_setup.c

Main fixes:

Add parentheses to avoid implicit operator precedence [Rule 12.1]

Fixed if statement conditional to be essentially boolean [Rule 14.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Voided non c-library functions whose return types are not used [Rule 17.7]

Bug 200272157

Change-Id: Ic3ab5a3de95aeb6d2265df940f7fb35ea0f19ab0
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra: gpcdma: driver for general purpose DMA

This patch adds the driver for the general purpose DMA hardware
block on newer Tegra SoCs. The GPCDMA is a special purpose DMA
used to speed up memory c

Tegra: gpcdma: driver for general purpose DMA

This patch adds the driver for the general purpose DMA hardware
block on newer Tegra SoCs. The GPCDMA is a special purpose DMA
used to speed up memory copy operations to/from DRAM and TZSRAM.

This patch introduces a macro 'USE_GPC_DMA' to allow platforms
to override CPU based memory operations.

Change-Id: I3170d409c83b77e785437b1002a8d70188fabbeb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: skip the BTB invalidate workaround for B01 SKUs

This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as
they have already been fixed in the hardware. To allow the .S file

Tegra210: skip the BTB invalidate workaround for B01 SKUs

This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as
they have already been fixed in the hardware. To allow the .S file to
include macros, add proper guards to tegra_platform.h.

Change-Id: I0826d3c54faeffc9cb0709331f47cbdf25d4b653
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

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Tegra186: memctrl_v2: Set MC clients ordering as per client needs

Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO)
based on the latest info received from HW team as a part

Tegra186: memctrl_v2: Set MC clients ordering as per client needs

Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO)
based on the latest info received from HW team as a part of BW issues debug.

SMMU Client config register are obsolete from T186. Clean up the unnecessary
register definitions and programming of these registers.
Cleanup unnecessary macros as well.

Change-Id: I0d28ae8842a33ed534f6a15bfca3c9926b3d46b2
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>

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Tegra210: memmap all the IRAM memory banks

This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the ba

Tegra210: memmap all the IRAM memory banks

This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the banks to avoid surprises.

Change-Id: Ia009a65d227ee50fbb23e511ce509daf41b877ee
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: setup: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

For

Tegra186: setup: fix defects flagged by MISRA scan

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Force operands of an operator to the same type category [Rule 10.4]

Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]

Change-Id: I4840c3122939f736113d61f1462af3bd7b0b5085
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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Tegra186: PM: fix MISRA defects in plat_psci_handlers.c

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

Tegra186: PM: fix MISRA defects in plat_psci_handlers.c

Main fixes:

Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]

convert object type to match the type of function parameters
[Rule 10.3]

Force operands of an operator to the same type category [Rule 10.4]

Fix implicit widening of composite assignment [Rule 10.6]

Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

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