1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_PRIVATE_H 8 #define TEGRA_PRIVATE_H 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <lib/psci/psci.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 17 #include <tegra_gic.h> 18 19 /******************************************************************************* 20 * Tegra DRAM memory base address 21 ******************************************************************************/ 22 #define TEGRA_DRAM_BASE ULL(0x80000000) 23 #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 24 25 /******************************************************************************* 26 * Struct for parameters received from BL2 27 ******************************************************************************/ 28 typedef struct plat_params_from_bl2 { 29 /* TZ memory size */ 30 uint64_t tzdram_size; 31 /* TZ memory base */ 32 uint64_t tzdram_base; 33 /* UART port ID */ 34 int32_t uart_id; 35 /* L2 ECC parity protection disable flag */ 36 int32_t l2_ecc_parity_prot_dis; 37 } plat_params_from_bl2_t; 38 39 /******************************************************************************* 40 * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 41 ******************************************************************************/ 42 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 43 44 /******************************************************************************* 45 * Struct describing parameters passed to bl31 46 ******************************************************************************/ 47 struct tegra_bl31_params { 48 param_header_t h; 49 image_info_t *bl31_image_info; 50 entry_point_info_t *bl32_ep_info; 51 image_info_t *bl32_image_info; 52 entry_point_info_t *bl33_ep_info; 53 image_info_t *bl33_image_info; 54 }; 55 56 /* Declarations for plat_psci_handlers.c */ 57 int32_t tegra_soc_validate_power_state(uint32_t power_state, 58 psci_power_state_t *req_state); 59 60 /* Declarations for plat_setup.c */ 61 const mmap_region_t *plat_get_mmio_map(void); 62 uint32_t plat_get_console_from_id(int32_t id); 63 void plat_gic_setup(void); 64 struct tegra_bl31_params *plat_get_bl31_params(void); 65 plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 66 67 /* Declarations for plat_secondary.c */ 68 void plat_secondary_setup(void); 69 int32_t plat_lock_cpu_vectors(void); 70 71 /* Declarations for tegra_fiq_glue.c */ 72 void tegra_fiq_handler_setup(void); 73 int tegra_fiq_get_intr_context(void); 74 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 75 76 /* Declarations for tegra_security.c */ 77 void tegra_security_setup(void); 78 void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 79 80 /* Declarations for tegra_pm.c */ 81 extern uint8_t tegra_fake_system_suspend; 82 83 void tegra_pm_system_suspend_entry(void); 84 void tegra_pm_system_suspend_exit(void); 85 int32_t tegra_system_suspended(void); 86 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); 87 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); 88 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); 89 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); 90 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 91 int32_t tegra_soc_prepare_system_reset(void); 92 __dead2 void tegra_soc_prepare_system_off(void); 93 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 94 const plat_local_state_t *states, 95 uint32_t ncpu); 96 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); 97 void tegra_cpu_standby(plat_local_state_t cpu_state); 98 int32_t tegra_pwr_domain_on(u_register_t mpidr); 99 void tegra_pwr_domain_off(const psci_power_state_t *target_state); 100 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); 101 void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 102 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); 103 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); 104 __dead2 void tegra_system_off(void); 105 __dead2 void tegra_system_reset(void); 106 int32_t tegra_validate_power_state(uint32_t power_state, 107 psci_power_state_t *req_state); 108 int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); 109 110 /* Declarations for tegraXXX_pm.c */ 111 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 112 int tegra_prepare_cpu_on_finish(unsigned long mpidr); 113 114 /* Declarations for tegra_bl31_setup.c */ 115 plat_params_from_bl2_t *bl31_get_plat_params(void); 116 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 117 void plat_early_platform_setup(void); 118 119 /* Declarations for tegra_delay_timer.c */ 120 void tegra_delay_timer_init(void); 121 122 void tegra_secure_entrypoint(void); 123 void tegra186_cpu_reset_handler(void); 124 125 /* Declarations for tegra_sip_calls.c */ 126 uintptr_t tegra_sip_handler(uint32_t smc_fid, 127 u_register_t x1, 128 u_register_t x2, 129 u_register_t x3, 130 u_register_t x4, 131 void *cookie, 132 void *handle, 133 u_register_t flags); 134 int plat_sip_handler(uint32_t smc_fid, 135 uint64_t x1, 136 uint64_t x2, 137 uint64_t x3, 138 uint64_t x4, 139 const void *cookie, 140 void *handle, 141 uint64_t flags); 142 143 #endif /* TEGRA_PRIVATE_H */ 144