1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TEGRA_PRIVATE_H 8 #define TEGRA_PRIVATE_H 9 10 #include <platform_def.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <lib/psci/psci.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 17 #include <tegra_gic.h> 18 19 /******************************************************************************* 20 * Tegra DRAM memory base address 21 ******************************************************************************/ 22 #define TEGRA_DRAM_BASE ULL(0x80000000) 23 #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 24 25 /******************************************************************************* 26 * Implementation defined ACTLR_EL1 bit definitions 27 ******************************************************************************/ 28 #define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0) 29 30 /******************************************************************************* 31 * Implementation defined ACTLR_EL2 bit definitions 32 ******************************************************************************/ 33 #define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0) 34 35 /******************************************************************************* 36 * Struct for parameters received from BL2 37 ******************************************************************************/ 38 typedef struct plat_params_from_bl2 { 39 /* TZ memory size */ 40 uint64_t tzdram_size; 41 /* TZ memory base */ 42 uint64_t tzdram_base; 43 /* UART port ID */ 44 int32_t uart_id; 45 /* L2 ECC parity protection disable flag */ 46 int32_t l2_ecc_parity_prot_dis; 47 } plat_params_from_bl2_t; 48 49 /******************************************************************************* 50 * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs 51 ******************************************************************************/ 52 DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) 53 54 /******************************************************************************* 55 * Struct describing parameters passed to bl31 56 ******************************************************************************/ 57 struct tegra_bl31_params { 58 param_header_t h; 59 image_info_t *bl31_image_info; 60 entry_point_info_t *bl32_ep_info; 61 image_info_t *bl32_image_info; 62 entry_point_info_t *bl33_ep_info; 63 image_info_t *bl33_image_info; 64 }; 65 66 /* Declarations for plat_psci_handlers.c */ 67 int32_t tegra_soc_validate_power_state(uint32_t power_state, 68 psci_power_state_t *req_state); 69 70 /* Declarations for plat_setup.c */ 71 const mmap_region_t *plat_get_mmio_map(void); 72 uint32_t plat_get_console_from_id(int32_t id); 73 void plat_gic_setup(void); 74 struct tegra_bl31_params *plat_get_bl31_params(void); 75 plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 76 77 /* Declarations for plat_secondary.c */ 78 void plat_secondary_setup(void); 79 int32_t plat_lock_cpu_vectors(void); 80 81 /* Declarations for tegra_fiq_glue.c */ 82 void tegra_fiq_handler_setup(void); 83 int tegra_fiq_get_intr_context(void); 84 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 85 86 /* Declarations for tegra_security.c */ 87 void tegra_security_setup(void); 88 void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 89 90 /* Declarations for tegra_pm.c */ 91 extern uint8_t tegra_fake_system_suspend; 92 93 void tegra_pm_system_suspend_entry(void); 94 void tegra_pm_system_suspend_exit(void); 95 int32_t tegra_system_suspended(void); 96 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); 97 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); 98 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); 99 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state); 100 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 101 int32_t tegra_soc_prepare_system_reset(void); 102 __dead2 void tegra_soc_prepare_system_off(void); 103 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, 104 const plat_local_state_t *states, 105 uint32_t ncpu); 106 void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state); 107 void tegra_cpu_standby(plat_local_state_t cpu_state); 108 int32_t tegra_pwr_domain_on(u_register_t mpidr); 109 void tegra_pwr_domain_off(const psci_power_state_t *target_state); 110 void tegra_pwr_domain_suspend(const psci_power_state_t *target_state); 111 void __dead2 tegra_pwr_domain_power_down_wfi(const psci_power_state_t *target_state); 112 void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state); 113 void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state); 114 __dead2 void tegra_system_off(void); 115 __dead2 void tegra_system_reset(void); 116 int32_t tegra_validate_power_state(uint32_t power_state, 117 psci_power_state_t *req_state); 118 int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint); 119 120 /* Declarations for tegraXXX_pm.c */ 121 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 122 int tegra_prepare_cpu_on_finish(unsigned long mpidr); 123 124 /* Declarations for tegra_bl31_setup.c */ 125 plat_params_from_bl2_t *bl31_get_plat_params(void); 126 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 127 void plat_early_platform_setup(void); 128 129 /* Declarations for tegra_delay_timer.c */ 130 void tegra_delay_timer_init(void); 131 132 void tegra_secure_entrypoint(void); 133 void tegra186_cpu_reset_handler(void); 134 135 /* Declarations for tegra_sip_calls.c */ 136 uintptr_t tegra_sip_handler(uint32_t smc_fid, 137 u_register_t x1, 138 u_register_t x2, 139 u_register_t x3, 140 u_register_t x4, 141 void *cookie, 142 void *handle, 143 u_register_t flags); 144 int plat_sip_handler(uint32_t smc_fid, 145 uint64_t x1, 146 uint64_t x2, 147 uint64_t x3, 148 uint64_t x4, 149 const void *cookie, 150 void *handle, 151 uint64_t flags); 152 153 #endif /* TEGRA_PRIVATE_H */ 154