feat(aarch64): add DBGPRCR_EL1 register accessors

This is a small change adding accessor functions for the Debug Power
Control register (DBGPRCR_EL1) to the common architectural helpers.

Change-Id:

feat(aarch64): add DBGPRCR_EL1 register accessors

This is a small change adding accessor functions for the Debug Power
Control register (DBGPRCR_EL1) to the common architectural helpers.

Change-Id: I72261fbf0395d900347b46af320093ed946aa73d
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.

This change introduces the period prefix to all specialized section
names.

BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.

Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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refactor(mediatek): change the parameters of LPM API

Change the parameters of the LPM API for further extension.

Change-Id: Id8897c256c2118d00c6b9f3e7424ebc6100f02eb
Signed-off-by: Liju-Clr Chen <l

refactor(mediatek): change the parameters of LPM API

Change the parameters of the LPM API for further extension.

Change-Id: Id8897c256c2118d00c6b9f3e7424ebc6100f02eb
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>

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fix(mt8186): fix the DRAM voltage after the system resumes

The DRAM power supply must sustain at 0.8V after the system resumes.
Otherwise, unexpected errors would occur. Therefore, we update the
DRA

fix(mt8186): fix the DRAM voltage after the system resumes

The DRAM power supply must sustain at 0.8V after the system resumes.
Otherwise, unexpected errors would occur. Therefore, we update the
DRAM voltage to 0.8v in PMIC voltage wrap table.

BUG=b:253537849
TEST=Suspend Resume Test

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: Idd42d5a2d646468822e391e48d01d870c3b7f0d3

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fix(mt8186): fix EMI_MPU domain setting for DSP

Correct the domain setting for DSP. It should be 6.

BUG=b:249954378
TEST=audio is functional.

Change-Id: Ie79aa0dad3d2b1ef5de0f2acc51ded13b6f085ac
S

fix(mt8186): fix EMI_MPU domain setting for DSP

Correct the domain setting for DSP. It should be 6.

BUG=b:249954378
TEST=audio is functional.

Change-Id: Ie79aa0dad3d2b1ef5de0f2acc51ded13b6f085ac
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>

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fix(mt8186-emi-mpu): fix SCP permission

Hardware video decoding is not working after enabling EMI MPU protection
for SCP.

According to coreboot DEVAPC setting, SCP belongs to domain 4 instead of
do

fix(mt8186-emi-mpu): fix SCP permission

Hardware video decoding is not working after enabling EMI MPU protection
for SCP.

According to coreboot DEVAPC setting, SCP belongs to domain 4 instead of
domain 3. So correct the permission setting.

BUG=b:249954378
TEST=play video and see codec irq count is incrementing.

Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: If71de3eabf8682909f96924c159aa92f25deb96c

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feat(mt8186): add EMI MPU support for SCP and DSP

1. Enable domain D0 and D3 (SCP) access 0x50000000~0x5109FFFF.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:204229221
TEST=b

feat(mt8186): add EMI MPU support for SCP and DSP

1. Enable domain D0 and D3 (SCP) access 0x50000000~0x5109FFFF.
2. Enable domain D4 (DSP & AFE) access 0x60000000~0x610FFFFF.

BUG=b:204229221
TEST=build pass

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: I6a7d2eafaaa7a558829a0d741dfb3307885e3b98

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refator(mediatek): move common definitions of pmic wrap to common folder

Some definitions can be shared among mt8192, mt8195, and
mt8186, so move them to pmic_wrap_init_common.h.

Signed-off-by: Bo-

refator(mediatek): move common definitions of pmic wrap to common folder

Some definitions can be shared among mt8192, mt8195, and
mt8186, so move them to pmic_wrap_init_common.h.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I992b61a47a84039fe8c246e2ff75721c57ee41a5

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feat(mediatek): move mtk_cirq.c drivers to cirq folder

To use cirq drivers more easier, we place mtk_cirq.c and mtk_cirq.h
to common/drivers/cirq.

We also rename mtk_cirq.c/h to mt_cirq.c/h for con

feat(mediatek): move mtk_cirq.c drivers to cirq folder

To use cirq drivers more easier, we place mtk_cirq.c and mtk_cirq.h
to common/drivers/cirq.

We also rename mtk_cirq.c/h to mt_cirq.c/h for consistency with other
driver folders.

TEST=build pass for mt8192/mt8195/mt8186
BUG=b:236331724

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I71bc442f00b16fb4031260937982c0496fcaaea0

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fix(mt8186): move SSPM base register definition to platform_def.h

- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.

Sig

fix(mt8186): move SSPM base register definition to platform_def.h

- move base register definition to platform_def.h for maintenance.
- SSPM_MBOX_3_BASE is redefined, use SSPM_MBOX_BASE instead.

Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: Ibb0291ce7b7426068392e90bd70f29d1a90d5297

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