feat(imx8ulp): adjust the voltage when sys dvfs enabled

When system level DVFS is enabled, voltage can be changed to
optimize the power consumption.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Revi

feat(imx8ulp): adjust the voltage when sys dvfs enabled

When system level DVFS is enabled, voltage can be changed to
optimize the power consumption.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Idfa0e637402078f3daf6e7c4ea1abb9af7675494

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feat(imx8ulp): enable the DDR frequency scaling support

Enable the DDR frequency scaling support on i.MX8ULP.
Normally, the freq_index define is as below:

0: boot frequency;
1: low frequency(PLL

feat(imx8ulp): enable the DDR frequency scaling support

Enable the DDR frequency scaling support on i.MX8ULP.
Normally, the freq_index define is as below:

0: boot frequency;
1: low frequency(PLL bypassed);
2. high frequency(PLL ON).

Currently, DDR DFS only do frequency switching between
Low freq and high freq.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I3acd8bdf75e2dd6dff645b9f597dcfc0a756c428

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fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only

After resume from APD power down, XRDC is initialized by S400 but
the PAC2 and MSC0-2 are not configured, so only DBD owner can acc

fix(imx8ulp): fix suspend/resume issue when DBD owner is s400 only

After resume from APD power down, XRDC is initialized by S400 but
the PAC2 and MSC0-2 are not configured, so only DBD owner can access
the resources.

We have to move GPIO restore after TFA XRDC reinit and configure
PDAC for PCC5 before enabling eDMA2 MP clock

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I82748de080151b0bdf1cace092b7892a1e402a27

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feat(imx8ulp): update XRDC for ELE to access DDR with CA35 DID

In order to isolate application memories, ELE FW introduces
a new policy which mimics the requestor attributes (DID, TZ).
So ELE config

feat(imx8ulp): update XRDC for ELE to access DDR with CA35 DID

In order to isolate application memories, ELE FW introduces
a new policy which mimics the requestor attributes (DID, TZ).
So ELE configures SCM to access to external memory with CA35 DID
when CA35 request something from ELE.

Because ELE accesses DDR through NIC_LPAV, the XRDC MRC6 must be
configured for CA35 DID 7 to authorize the access.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I9e91a1b2798e8d15127d1bfa9aa0ffc612fd8981

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feat(imx8ulp): add memory region policy

set the memory region policy for secure heap(0xA9600000 ~ 0xAF600000),
it can only be RWX by secure master. At the same time, restrict G2D
and DCnano(domain 3

feat(imx8ulp): add memory region policy

set the memory region policy for secure heap(0xA9600000 ~ 0xAF600000),
it can only be RWX by secure master. At the same time, restrict G2D
and DCnano(domain 3) to write non-secure memory when they are set as
secure master.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If53e130eaeb1ac867ee56e4af04e3be29dec9857

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feat(imx8ulp): protect TEE region for secure access only

Using XRDC MRC4/5/6 to restrict the secure access for TEE DDR
memory to protect TEE.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng

feat(imx8ulp): protect TEE region for secure access only

Using XRDC MRC4/5/6 to restrict the secure access for TEE DDR
memory to protect TEE.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic161df6a98ded23b9a74d552717fc5dcc1ee2ae8

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feat(imx8ulp): add trusty support

Support trusty on imx8ulp.

Signed-off-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I7ada2557023e271a721d50bfe7fd20b5f01cb128

feat(imx8ulp): add OPTEE support

Add opteed support for imx8ulp.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Iddf6f164b7146332e99de42

feat(imx8ulp): add OPTEE support

Add opteed support for imx8ulp.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Iddf6f164b7146332e99de42fcbbf9c892eb1d994

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feat(imx8ulp): update the upower config for power optimization

Enable the AFBB by default for active mode when APD side wakeup
from low power mode to align with the first time boot up.

Update the p

feat(imx8ulp): update the upower config for power optimization

Enable the AFBB by default for active mode when APD side wakeup
from low power mode to align with the first time boot up.

Update the power mode configs to force shutdown all the
necessary power switches to optimize the power consumption.

To reduce the pad power consumption, put all the pad into
OFF mode to save more power. the PTD's compensation should
also be disabled in low power mode to save more power.

when APD enters PD mode, the LDO1(used by DDR) can be shutdown
to save power. when APD enters DPD mode, the BUCK3(supply for
APD/LPAV) can be shutdown to save power.

In single boot mode, When APD enters DPD mode, buck3 will
shutdown, LDO1 should be off to save more power as the DDR
controller has lost power.

In dualboot mode, the LPAV is owned by RTD side. When APD enters
low power mode, APD side should not config those PMIC regulators
that used by the resource owned by RTD side.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ie5e9b428f85345b81744313a8fb93bfc27e0dd71

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feat(imx8ulp): allow RTD to reset APD through MU

Clear HRM bit in MU0_B CCR0 register to allow RTD to reset APD.
The action needs at both ATF init and APD resume.

Signed-off-by: Ye Li <ye.li@nxp.co

feat(imx8ulp): allow RTD to reset APD through MU

Clear HRM bit in MU0_B CCR0 register to allow RTD to reset APD.
The action needs at both ATF init and APD resume.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I2475e34b13f57818580a478ab567bfb9fc6cf174

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feat(imx8ulp): not power off LPAV PD when LPAV owner is RTD

Upower will check the LPAV ownership when power off the SRAM or PS.
if the LPAV owner is not APD, then the power off will return failure.

feat(imx8ulp): not power off LPAV PD when LPAV owner is RTD

Upower will check the LPAV ownership when power off the SRAM or PS.
if the LPAV owner is not APD, then the power off will return failure.
Add similar checking in SCMI PD driver to skip the power off to avoid
failure print causing suspend/resume not work.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I9dc657c2277129ac90a792232f734c08fca5f997

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feat(imx8ulp): add system power off support

On i.MX8ULP, we need to use the APD deep power down(DPD) mode
to support the system power off function. when APD enter
power off mode, only the RTD can re

feat(imx8ulp): add system power off support

On i.MX8ULP, we need to use the APD deep power down(DPD) mode
to support the system power off function. when APD enter
power off mode, only the RTD can re-kick it and boot from ROM.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ifb42db0a7cf87b932160c59b47eca4d0f08f8cdf

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feat(imx8ulp): add APD power down mode(PD) support in system suspend

The APD can be put into PD mode when linux suspend(mem). This patch
add the support for it. As the whole AP domain's context will

feat(imx8ulp): add APD power down mode(PD) support in system suspend

The APD can be put into PD mode when linux suspend(mem). This patch
add the support for it. As the whole AP domain's context will be lost,
so we must save the necessary HW module states before entering PD mode,
and we need to restore those contexts when system wake up. Fot details
about which HW module's state will be lost, please refer to the RM.

When APD enter PD mode, only the wakeup event connected to the WUU
can wakeup APD successfully. The upower wakeup source is used to
wakeup APD by RTD due to the factor that the MU between A core & M
core is not connected into WUU to generate wakeup event.

as the SRAM0 will be power down when APD enters PD mode, so we
need to re-init the scmi channels(resides in the SRAM0). otherwise
the SCMI can NOT work anymore.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I44b0cdc8397e5d6a82081ea6746542e9fa4b9fc1

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feat(imx8ulp): add the basic support for idle & system suspned

Add basic support for the cpuidle(cluster retention) and system
suspend support using the HW sleep mode.

When system enter low power m

feat(imx8ulp): add the basic support for idle & system suspned

Add basic support for the cpuidle(cluster retention) and system
suspend support using the HW sleep mode.

When system enter low power mode after doing reboot twice, APD
will be failed to exit from low power mode successfully. it is
because that after secondary reboot, upower will modify the default
power switch config, then DDR will be off wrongly. So config the
low power mode info explicitly before APD entering any low power
mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ib68bfdfd4b925541e343aef4a5296a542451f86b

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feat(imx8ulp): enable 512KB cache after resume on imx8ulp

The L2 cache size config will be reset to default 256KB,
So we need to switch to 512KB after resume to make sure
the L2 cache size is same a

feat(imx8ulp): enable 512KB cache after resume on imx8ulp

The L2 cache size config will be reset to default 256KB,
So we need to switch to 512KB after resume to make sure
the L2 cache size is same as before suspend.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ifd9b3e01829fbd7b1ae4ba00611359330f1a4f83

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feat(imx8ulp): add the initial XRDC support

Add the initial xRDC support on i.MX8ULP.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.

feat(imx8ulp): add the initial XRDC support

Add the initial xRDC support on i.MX8ULP.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I93ea8e2cebb049e6f20e71cfe50c7583a3228f38

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feat(imx8ulp): allocated caam did for the non secure world

JR1, JR2 and JR3 are available for use by the non secure
world. Setup the A35 core DID for these job rings.

Signed-off-by: Varun Sethi <v.

feat(imx8ulp): allocated caam did for the non secure world

JR1, JR2 and JR3 are available for use by the non secure
world. Setup the A35 core DID for these job rings.

Signed-off-by: Varun Sethi <v.sethi@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If64d4ce11ebff49a2405d8b561b344fcd7b2614f

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feat(imx8ulp): add i.MX8ULP basic support

Add the basic support for i.MX8ULP.

The i.MX 8ULP family of processors features NXP’s advanced
implementation of the dual Arm Cortex-A35 cores alongside
an

feat(imx8ulp): add i.MX8ULP basic support

Add the basic support for i.MX8ULP.

The i.MX 8ULP family of processors features NXP’s advanced
implementation of the dual Arm Cortex-A35 cores alongside
an Arm Cortex-M33. This combined architecture enables the
device to run a rich operating system (such as Linux) on
the Cortex-A35 core and an RTOS (such as FreeRTOS) on the
Cortex-M33 core. It also includes a Cadence Tensilica Fusion
DSP for low-power audio and a HiFi4 DSP for advanced audio
and machine learning applications.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I12df622b95960bcdf7da52e4c66470a700690e36

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Merge "fix(imx8mp): uncondtionally enable only the USB power domain" into integration

feat(imx8m): obtain boot image set for imx8mn/mp

In i.MX8MM/MQ it is possible to have two copies of bootloader in
SD/eMMC and switch between them. The switch is triggered either
by the BootROM in ca

feat(imx8m): obtain boot image set for imx8mn/mp

In i.MX8MM/MQ it is possible to have two copies of bootloader in
SD/eMMC and switch between them. The switch is triggered either
by the BootROM in case the bootloader image is faulty OR can be
enforced by the user, and there is API introduced in
9ce232fe ("feat(plat/imx8m): add SiP call for secondary boot"),
which leverages this SoC feature.

However neither i.MX8MP nor i.MX8MN have a dedicated bit
which indicates what boot image set is currently booted.
According to AN12853 [1] "i.MX ROMs Log Events", it is
possible to determine whether fallback event occurred
by parsing the BootROM event log. In case ROM event ID 0x51 is
present,fallback event did occur and secondary boot image was booted.

Knowing which boot image was booted might be useful for reliable
bootloader A/B updates, detecting fallback event might be used for
making decision if boot firmware rollback is required.

This patche introduces implementation, that replicates the same
imx_src_handler() behaviour as on i.MX8MM/MQ SoCs.

The code is based on original U-Boot implementation [2].

[1]: https://www.nxp.com/webapp/Download?colCode=AN12853
[2]: https://github.com/u-boot/u-boot/commit/a5ee05cf7180b411ffdf148ca8cb220c029f2e19

Change-Id: I9a4c5229aa0e53fa23b5261459da99cb3ce6bdbe
Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>

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fix(imx8mp): uncondtionally enable only the USB power domain

The i.MX8MP exists in multiple SKUs, some of which lack the NPU or VPU.
Yet, we unconditionally enable NPU and VPU power domains in upstr

fix(imx8mp): uncondtionally enable only the USB power domain

The i.MX8MP exists in multiple SKUs, some of which lack the NPU or VPU.
Yet, we unconditionally enable NPU and VPU power domains in upstream
TF-A, causing it to hang on such SoCs, unless patched.

Enabling all power domains is an idiosyncrasy of the i.MX8MP support,
which we don't have on i.MX8MQ, i.MX8MM or i.MX8MN. Therefore let's drop
unconditional powering on of all power domains.

As only exception, we will keep enabling the USB power domains. These
are enabled in the BootROM if booting over SDPS and boot firmware may
expect them to be enabled for non-SDPS recovery too. As USB is
available unconditionally on the current i.MX8MP variants, this is
deemed acceptable and reduces the chance of breaking existing systems.

Fixes: a775ef25c312 ("plat: imx8mp: Add the basic support for i.MX8MP")
Change-Id: Idc6e8f770d240f4d929dffa91f9ccf8c476c6c12
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

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feat(imx8m): make bl33 start configurable via PRELOADED_BL33_BASE

The TF-A does have a official PRELOADED_BL33_BASE define which is used
to tell the TF-A where to jump and that no bl33 loading is re

feat(imx8m): make bl33 start configurable via PRELOADED_BL33_BASE

The TF-A does have a official PRELOADED_BL33_BASE define which is used
to tell the TF-A where to jump and that no bl33 loading is requied. Use
this to make the platform specific PLAT_NS_IMAGE_OFFSET configurable.

This becomes necessary if one would like to place the bl33 code to other
places.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I9d462c0e9df8e6d2ad78ee770bfa59e680739a51

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feat(imx8m): add 3600 MTps DDR PLL rate

Add 3600 MTps DRAM and its 900 MHz PLL setting M=300 P=8 S=0 , so
24 MHz * 300 / 8 / 2^0 = 900 MHz ~ 3600 MTps (x4) .

Signed-off-by: Marek Vasut <marex@denx.

feat(imx8m): add 3600 MTps DDR PLL rate

Add 3600 MTps DRAM and its 900 MHz PLL setting M=300 P=8 S=0 , so
24 MHz * 300 / 8 / 2^0 = 900 MHz ~ 3600 MTps (x4) .

Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: If2743827294efc0f981718f04b772cc462846195

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fix(imx8m): align 3200 MTps rate with U-Boot

The 3200 MTps DRAM and its 800 MHz PLL setting in U-Boot is set to
M=300 P=9 S=0 , so 24 MHz * 300 / 9 / 2^0 = 800 MHz ~ 3200 MTps (x4) .
Make sure the P

fix(imx8m): align 3200 MTps rate with U-Boot

The 3200 MTps DRAM and its 800 MHz PLL setting in U-Boot is set to
M=300 P=9 S=0 , so 24 MHz * 300 / 9 / 2^0 = 800 MHz ~ 3200 MTps (x4) .
Make sure the PLL settings are aligned across software components.

Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: I163f81696be213acf6ecebe89ff2c76d41484cc5

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fix(imx8m): handle 3734 in addition to 3733 and 3732 MTps rates

The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another roundin

fix(imx8m): handle 3734 in addition to 3733 and 3732 MTps rates

The new MX8M DDR tool 3.31 now generates a programming file which uses
data rate 3734 instead of 3733 or 3732 . Handle another rounding option .

Signed-off-by: Marek Vasut <marex@denx.de>
Change-Id: I97a69650c12d78dfff9dcdb23e27fd6590f57fc0

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