Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): suppo

Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration

* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): support BL32 (OP-TEE)

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Merge "fix(arm): derive RMM bank size from payload" into integration

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa)

Merge changes from topic "mb/lfa-rmm-test" into integration

* changes:
fix(rmmd): avoid race conditions in CPU finish
fix(arm): move lfa componet header to common and fix the helper
chore(lfa): rename component_id to lfa_component_id

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fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `

fix(security): add clrbhb support

TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/

On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.

Ref- https://developer.arm.com/documentation/102898/0108/

Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(cpus): add support for venom cpu

Add basic CPU library code to support Venom CPU

Change-Id: I84d4cb77b175812811a17e55b4b290585e05d216
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

feat(rdaspen): support BL32 (OP-TEE)

Configure SPMC constants and Secure memory partition to boot BL32
image.

This also fixes the build to automatically accommodate BL33 if
BL32 base is not specif

feat(rdaspen): support BL32 (OP-TEE)

Configure SPMC constants and Secure memory partition to boot BL32
image.

This also fixes the build to automatically accommodate BL33 if
BL32 base is not specified, and removes a redundant entry for BL31
in platform definitions for mmap entries aswell.

Change-Id: I6a3ec97c8f41d6bddc4f20b6edc088a46e2caa75
Signed-off-by: Archish Venkatesh <Archish.Venkatesh@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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Merge "feat(cpus): add support for Dionysus cpu library" into integration

Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platfor

Merge changes from topic "xl/fwu-trial-run" into integration

* changes:
fix(fwu): fwu NV ctr upgraded on trial run
feat(docs): platform hook for whether NV ctr is shared
feat(fwu): add platform hook for shared NV ctr

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feat(rdaspen): add support for configurable platform's CPU topology

- Add support for passing build time platform's CPU topology, which
defines the number of clusters and CPUs in the platform.
- A

feat(rdaspen): add support for configurable platform's CPU topology

- Add support for passing build time platform's CPU topology, which
defines the number of clusters and CPUs in the platform.
- Adjust the platform's power domain topology based on the passed
build time topology. If no build time topology was provided,
default topology will be used.

Change-Id: Ic80b308ab6d4c98139723021566d54be02b7d125
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>

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feat(rdaspen): scmi gracefully shutdown system

In RD-Aspen, RSE shall be responsible for system shutdown. When TF-A
send a graceful SCMI system power set command to SCP, SCP will not
execute the shu

feat(rdaspen): scmi gracefully shutdown system

In RD-Aspen, RSE shall be responsible for system shutdown. When TF-A
send a graceful SCMI system power set command to SCP, SCP will not
execute the shutdown but notify RSE runtime.

RD-Aspen enable the graceful flag of css_scp_system_off in
platform.mk.

Change-Id: I80967e1d2e85193dd98f626e4c729ac722251a53
Signed-off-by: Jun Wu <jun.wu@arm.com>

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fix(rdaspen): enable CPU feature runtime checking

Enable runtime feature detection for FEAT_AMU, FEAT_ECV, FEAT_FGT,
and FEAT_MTE2

These features were previously unconditionally enabled (=1) in the

fix(rdaspen): enable CPU feature runtime checking

Enable runtime feature detection for FEAT_AMU, FEAT_ECV, FEAT_FGT,
and FEAT_MTE2

These features were previously unconditionally enabled (=1) in the build
configuration, causing TF-A to initialize their contexts regardless of
actual CPU support in emulation implementations.

Set them to "2" to enable runtime feature detection instead.

With this change, TF-A checks the ID registers before accessing related
system registers or programming SCR_EL3 bits, avoiding register accesses
on CPUs that lack these features. This primarily addresses issues seen
in emulation environments with incomplete feature support.

Change-Id: I7f333245c60685544d925c24556358724a776082
Signed-off-by: Peter Hoyes <peter.hoyes@arm.com>

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Merge "feat(arm): load config after GPT FIP offset" into integration

feat(fwu): add platform hook for shared NV ctr

The NV ctr should not update when it is shared among
Bl1 and BL2. This is platform specific, therefore add
a platform hook to query the platform for th

feat(fwu): add platform hook for shared NV ctr

The NV ctr should not update when it is shared among
Bl1 and BL2. This is platform specific, therefore add
a platform hook to query the platform for this infor-
mation.

Change-Id: Ib180c8e6a183f7aaa7586e3f008273860d55b414
Signed-off-by: Xialin Liu <xialin.liu@arm.com>

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Merge "fix(tc): force specifying TARGET_PLATFORM" into integration

feat(arm): load config after GPT FIP offset

When ARM_GPT_SUPPORT is enabled and the FIP resides inside a GPT
partition, arm_bl2_el3_plat_config_load() may try to load a random
FIP at base address 0,

feat(arm): load config after GPT FIP offset

When ARM_GPT_SUPPORT is enabled and the FIP resides inside a GPT
partition, arm_bl2_el3_plat_config_load() may try to load a random
FIP at base address 0, failing to find the actual FIP.

Resolve the FIP from the GPT partition table first and compute the
offset when ARM_GPT_SUPPORT is set, before calling
arm_bl2_el3_plat_config_load() to load the platform config from
the FIP itself.

Change-Id: I5c9a461961c5167b816d5fb632cceb76f1439d83
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(arm): derive RMM bank size from payload

Compute the RMM bank size as half of the RMM payload size instead of
using a hardcoded value. This removes duplication and keeps the bank
size automatical

fix(arm): derive RMM bank size from payload

Compute the RMM bank size as half of the RMM payload size instead of
using a hardcoded value. This removes duplication and keeps the bank
size automatically in sync with payload size changes.

Change-Id: I064390ec50115929bf6248344bf08a19fbc15344
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(arm): move lfa componet header to common and fix the helper

Move the FVP LFA component definitions to include/plat/arm/common/
so they can be shared by all Arm platforms, and update include
path

fix(arm): move lfa componet header to common and fix the helper

Move the FVP LFA component definitions to include/plat/arm/common/
so they can be shared by all Arm platforms, and update include
paths accordingly.

On FVP, rename the input parameter to lfa_component_id to match
the function declaration, and fix callers to pass the component
ID (not image_id) to the prime-complete helper.

Change-Id: Ia1485096819d6523c4bee14c602cbde3c6e144ef
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(cpus): add support for Dionysus cpu library

Add basic CPU library code to support the Dionysus CPU.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I4e6b3c7e7369b7cbf0

feat(cpus): add support for Dionysus cpu library

Add basic CPU library code to support the Dionysus CPU.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I4e6b3c7e7369b7cbf0e18d295e5ef5352f621e44

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fix(tc): force specifying TARGET_PLATFORM

tc platform.mk has assumptions about TARGET_PLATFORM to be properly
defined.

For PLAT=tc if not specifying TARGET_PLATFORM on build command line, it
emits

fix(tc): force specifying TARGET_PLATFORM

tc platform.mk has assumptions about TARGET_PLATFORM to be properly
defined.

For PLAT=tc if not specifying TARGET_PLATFORM on build command line, it
emits the cryptic error message:

expr: syntax error: unexpected argument \u20182\u2019
plat/arm/board/tc/platform.mk:75: *** Platform tc is no longer available.. Stop.

Add an assert such that the error becomes:

plat/arm/board/tc/platform.mk:9: *** TARGET_PLATFORM must not be empty. Stop.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: If53a01b537768a806495d8dc1c5096059eafa490

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Merge changes Ifbc5ab02,Ib9002609,I0276257d into integration

* changes:
fix(fvp): initialise the event log's size to avoid using gibberish values
fix(tsp): keep the tsp D128 unaware, not the dis

Merge changes Ifbc5ab02,Ib9002609,I0276257d into integration

* changes:
fix(fvp): initialise the event log's size to avoid using gibberish values
fix(tsp): keep the tsp D128 unaware, not the dispatcher
fix(dice): prevent compiler warnings

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feat(cpufeat): enable FEAT_PFAR support

Implement support for FEAT_PFAR, which introduces the PFAR_ELx system
register, recording the faulting physical address for some aborts.
Those system register

feat(cpufeat): enable FEAT_PFAR support

Implement support for FEAT_PFAR, which introduces the PFAR_ELx system
register, recording the faulting physical address for some aborts.
Those system registers are trapped by the SCR_EL3.PFARen bit, so set the
bit for the non-secure world context to allow OSes to use the feature.

This is controlled by the ENABLE_FEAT_PFAR build flag, which follows the
usual semantics of 2 meaning the feature being runtime detected.
Let the default for this flag be 0, but set it to 2 for the FVP.

Change-Id: I5c9ae750417e75792f693732df3869e02b6e4319
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "feat(cpufeat): enable FEAT_AIE support" into integration

fix(fvp): initialise the event log's size to avoid using gibberish values

The event log's DT bindings only specify the lower 32 bits of the event
log's size, but the size is held in a 64 bit variabl

fix(fvp): initialise the event log's size to avoid using gibberish values

The event log's DT bindings only specify the lower 32 bits of the event
log's size, but the size is held in a 64 bit variable on stack. When
conditions are right, the uninitialised upper 32 bits may contain
gibberish that throws off our computations, leading to faults.

Change-Id: Ifbc5ab027aac4e8899fea962656b07960b9b00b9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(dice): prevent compiler warnings

LTO builds make the compiler observe possible unitialised accesses.
That's not the case, but calm it down with a 0. It also doesn't like the
declaration mismatch

fix(dice): prevent compiler warnings

LTO builds make the compiler observe possible unitialised accesses.
That's not the case, but calm it down with a 0. It also doesn't like the
declaration mismatch in tc so bring it in line.

Change-Id: I0276257d05d1cb1d4f7e1e0d914c48c8ab3d308d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "gr/cpu_lib" into integration

* changes:
feat(cpus): add support for caddo cpu
feat(cpus): add support for veymont cpu