| 058efeef | 07-Nov-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
GICv2: Fix populating PE target data
This patch brings in the following fixes:
- The per-PE target data initialized during power up needs to be
flushed so as to be visible to other PEs.
-
GICv2: Fix populating PE target data
This patch brings in the following fixes:
- The per-PE target data initialized during power up needs to be
flushed so as to be visible to other PEs.
- Setup per-PE target data for the primary PE as well. At present,
this was only setup for secondary PEs when they were powered on.
Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| 9500d5a4 | 09-Nov-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1148 from antonio-nino-diaz-arm/an/spm
Introduce Secure Partition Manager |
| e29efeb1 | 09-Nov-2017 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
SPM: FVP: Introduce port of SPM
This initial port of the Secure Partitions Manager to FVP supports BL31
in both SRAM and Trusted DRAM.
A document with instructions to build the SPM has been added.
SPM: FVP: Introduce port of SPM
This initial port of the Secure Partitions Manager to FVP supports BL31
in both SRAM and Trusted DRAM.
A document with instructions to build the SPM has been added.
Change-Id: I4ea83ff0a659be77f2cd72eaf2302cdf8ba98b32
Co-authored-by: Douglas Raillard <douglas.raillard@arm.com>
Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: Achin Gupta <achin.gupta@arm.com>
Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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| 92c5066c | 06-Nov-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1153 from robertovargas-arm/fix-macros
Avoid use of undefined macros |
| 3de7d58e | 03-Nov-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1137 from soby-mathew/sm/arm_plat_en_gicv3_save
Enable GICv3 save for ARM platforms |
| d58f3cac | 20-Oct-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
Always define ARM_TSP_RAM_LOCATION_ID
ARM_TSP_RAM_LOCATION_ID was defined only in AARCH64, but the macro
was also used in AARCH32, and it meant that it was taking the value 0,
which happened to equa
Always define ARM_TSP_RAM_LOCATION_ID
ARM_TSP_RAM_LOCATION_ID was defined only in AARCH64, but the macro
was also used in AARCH32, and it meant that it was taking the value 0,
which happened to equal ARM_TRUSTED_SRAM_ID.
Change-Id: If9f4dbee1a2ba15e7806f2a03305b554bd327363
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 9b1eae96 | 13-Oct-2017 |
Qixiang Xu <qixiang.xu@arm.com> |
plat/arm: enlarge the BL2 size on Arm platforms when TBB is enabled
For Trusted Board Boot, BL2 needs more space to support the ECDSA
and ECDSA+RSA algorithms.
Change-Id: Ie7eda9a1315ce836dbc6d18d6
plat/arm: enlarge the BL2 size on Arm platforms when TBB is enabled
For Trusted Board Boot, BL2 needs more space to support the ECDSA
and ECDSA+RSA algorithms.
Change-Id: Ie7eda9a1315ce836dbc6d18d6588f8d17891a92d
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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| 7ca267bd | 13-Oct-2017 |
Qixiang Xu <qixiang.xu@arm.com> |
plat/arm: change the default option of ARM_TSP_RAM_LOCATION
On Arm standard platforms, it runs out of SRAM space when TBB is
enabled, so the TSP default location is changed to dram when TBB
is enabl
plat/arm: change the default option of ARM_TSP_RAM_LOCATION
On Arm standard platforms, it runs out of SRAM space when TBB is
enabled, so the TSP default location is changed to dram when TBB
is enabled.
Change-Id: I516687013ad436ef454d2055d4e6fce06e467044
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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| f911e229 | 21-Oct-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1131 from jeenu-arm/gic-migrate
Migrate upstream platforms to using interrupt properties |
| 623c4377 | 21-Oct-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1130 from jeenu-arm/gic-patches
New GIC APIs and specifying interrupt propertes |
| b2c363b1 | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: Migrate to using interrupt properties
An earlier patch added provision for the platform to provide secure
interrupt properties. ARM platforms already has a list of interrupts
that fal
ARM platforms: Migrate to using interrupt properties
An earlier patch added provision for the platform to provide secure
interrupt properties. ARM platforms already has a list of interrupts
that fall into different secure groups.
This patch defines macros that enumerate interrupt properties in the
same fashion, and points the driver driver data to a list of interrupt
properties rather than list of secure interrupts on ARM platforms. The
deprecated interrupt list definitions are however retained to support
legacy builds.
Configuration applied to individual interrupts remain unchanged, so no
runtime behaviour change expected.
NOTE: Platforms that use the arm/common function
plat_arm_gic_driver_init() must replace their PLAT_ARM_G1S_IRQS and
PLAT_ARM_G0_IRQS macro definitions with PLAT_ARM_G1S_IRQ_PROPS and
PLAT_ARM_G0_IRQ_PROPS macros respectively, using the provided
INTR_PROP_DESC macro.
Change-Id: I24d643b83e3333753a3ba97d4b6fb71e16bb0952
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| dea417cd | 22-Sep-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
ARM platforms: supply per-PE target mask array
Call the GICv2 driver API to initialise per-PE target mask.
Change-Id: Idc7eb0d906a5379f4c05917af05c90613057ab97
Signed-off-by: Jeenu Viswambharan <je
ARM platforms: supply per-PE target mask array
Call the GICv2 driver API to initialise per-PE target mask.
Change-Id: Idc7eb0d906a5379f4c05917af05c90613057ab97
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| b48ae263 | 16-Aug-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
reset2: Add css_system_reset2()
This function implements the platform dependant part of PSCI system
reset2 for CSS platforms using SCMI.
Change-Id: I724389decab484043cadf577aeed96b349c1466d
Signed-
reset2: Add css_system_reset2()
This function implements the platform dependant part of PSCI system
reset2 for CSS platforms using SCMI.
Change-Id: I724389decab484043cadf577aeed96b349c1466d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| ed3c0ef8 | 31-Jul-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
scp: Introduce css_scp_system_off() function
The common implementation of css_scp_sys_shutdown and
css_scp_warm_reset is refactored into a new function,
css_scp_system_off() that allows the desired
scp: Introduce css_scp_system_off() function
The common implementation of css_scp_sys_shutdown and
css_scp_warm_reset is refactored into a new function,
css_scp_system_off() that allows the desired power state to be
specified.
The css_scp_system_off can be used in the implementation of
SYSTEM_RESET2 for PSCI v1.1.
Change-Id: I161e62354d3d75f969b8436d794335237520a9a4
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| e35a3fb5 | 11-Oct-2017 |
Soby Mathew <soby.mathew@arm.com> |
ARM platforms: enable GICv3 state save/restore
Provides GICv3 save/restore feature to arm_system_pwr_domain_resume and
arm_system_pwr_domain_save functions.
Introduce FVP PSCI power level 3 (System
ARM platforms: enable GICv3 state save/restore
Provides GICv3 save/restore feature to arm_system_pwr_domain_resume and
arm_system_pwr_domain_save functions.
Introduce FVP PSCI power level 3 (System level) support. This is solely
done to provide example code on how to use the GICv3 save and restore
helpers.
Also make CSS GICv3 platforms power off the Redistributor on SYSTEM
SUSPEND as its state is saved and restored.
Change-Id: I0d852f3af8824edee1a17c085cf593ddd33a4e77
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Co-Authored-by: Douglas Raillard <douglas.raillard@arm.com>
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| a22dffc6 | 05-Oct-2017 |
Soby Mathew <soby.mathew@arm.com> |
ARM platforms: Add support for EL3 TZC memory region
Some recent enhancements to EL3 runtime firmware like support for
save and restoring GICv3 register context during system_suspend
necessitates ad
ARM platforms: Add support for EL3 TZC memory region
Some recent enhancements to EL3 runtime firmware like support for
save and restoring GICv3 register context during system_suspend
necessitates additional data memory for the firmware. This patch
introduces support for creating a TZC secured DDR carveout for use
by ARM reference platforms. A new linker section `el3_tzc_dram` is
created using platform supplied linker script and data marked with
the attribute `arm_el3_tzc_dram` will be placed in this section.
The FVP makefile now defines the `PLAT_EXTRA_LD_SCRIPT` variable to
allow inclusion of the platform linker script by the top level BL31
linker script.
Change-Id: I0e7f4a75a6ac51419c667875ff2677043df1585d
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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| ebf1ca10 | 13-Jul-2017 |
Soby Mathew <soby.mathew@arm.com> |
GICv3: add functions for save and restore
During system suspend, the GICv3 Distributor and Redistributor context
can be lost due to power gating of the system power domain. This means
that the GICv3
GICv3: add functions for save and restore
During system suspend, the GICv3 Distributor and Redistributor context
can be lost due to power gating of the system power domain. This means
that the GICv3 context needs to be saved prior to system suspend and
restored on wakeup. Currently the consensus is that the Firmware should
be in charge of this. See tf-issues#464 for more details.
This patch introduces helper APIs in the GICv3 driver to save and
restore the Distributor and Redistributor contexts. The GICv3 ITS
context is not considered in this patch because the specification says
that the details of ITS power management is implementation-defined.
These APIs are expected to be appropriately invoked by the platform
layer during system suspend.
Fixes ARM-software/tf-issues#464
Change-Id: Iebb9c6770ab8c4d522546f161fa402d2fe02ec00
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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| c64d1345 | 04-Oct-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1109 from robertovargas-arm/mem_protect
Mem protect |
| cb2cfae3 | 04-Oct-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1115 from jeenu-arm/tsp-mt
TSP: Support multi-threading CPUs on FVP |
| 5e4ca661 | 03-Oct-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
TSP: Support multi-threading CPUs on FVP
Commit 11ad8f208db42f7729b0ce2bd16c631c293e665c added supporting
multi-threaded CPUs on FVP platform, including modifications for
calculating CPU IDs. This p
TSP: Support multi-threading CPUs on FVP
Commit 11ad8f208db42f7729b0ce2bd16c631c293e665c added supporting
multi-threaded CPUs on FVP platform, including modifications for
calculating CPU IDs. This patch imports the strong definition of the
same CPU ID calculation on FVP platform for TSP.
Without this patch, TSP on FVP was using the default CPU ID calculation,
which would end up being wrong on CPUs with multi-threading.
Change-Id: If67fd492dfce1f57224c9e693988c4b0f89a9a9a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| b8fa2ed5 | 02-Oct-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1107 from geesun/qx/add_ecdsa_support
Add support for TBBR using ECDSA keys in ARM platforms |
| b09ba056 | 08-Aug-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
mem_protect: Add DRAM2 to the list of mem protected ranges
On ARM platforms, the maximum size of the address space is limited
to 32-bits as defined in arm_def.h. In order to access DRAM2, which
is d
mem_protect: Add DRAM2 to the list of mem protected ranges
On ARM platforms, the maximum size of the address space is limited
to 32-bits as defined in arm_def.h. In order to access DRAM2, which
is defined beyond the 32-bit address space, the maximum address space
is increased to 36-bits in AArch64. It is possible to increase the
virtual space for AArch32, but it is more difficult and not supported
for now.
NOTE - the actual maximum memory address space is platform dependent
and is checked at run-time by querying the PARange field in the
ID_AA64MMFR0_EL1 register.
Change-Id: I6cb05c78a63b1fed96db9a9773faca04a5b93d67
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| f145403c | 03-Aug-2017 |
Roberto Vargas <roberto.vargas@arm.com> |
mem_protect: Add mem_protect support in Juno and FVP for DRAM1
mem_protect needs some kind of non-volatile memory because it has
to remember its state across reset and power down events.
The most su
mem_protect: Add mem_protect support in Juno and FVP for DRAM1
mem_protect needs some kind of non-volatile memory because it has
to remember its state across reset and power down events.
The most suitable electronic part for this feature is a NVRAM
which should be only accesible from the secure world. Juno and
FVP lack such hardware and for this reason the MEM_PROTECT
functionality is implemented with Flash EEPROM memory on both
boards, even though this memory is accesible from the non-secure
world. This is done only to show a full implementation of
these PSCI features, but an actual system shouldn't use a
non-secure NVRAM to implement it.
The EL3 runtime software will write the mem_protect flag and BL2
will read and clear the memory ranges if enabled. It is done in
BL2 because it reduces the time that TF needs access to the full
non-secure memory.
The memory layout of both boards is defined using macros which
take different values in Juno and FVP platforms. Generic platform
helpers are added that use the platform specific macros to generate
a mem_region_t that is valid for the platform.
Change-Id: I2c6818ac091a2966fa07a52c5ddf8f6fde4941e9
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
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| 9db9c65a | 24-Aug-2017 |
Qixiang Xu <qixiang.xu@arm.com> |
Add support for TBBR using ECDSA keys in ARM platforms
- fixed compile error when KEY_ALG=ecdsa
- add new option ecdsa for TF_MBEDTLS_KEY_ALG
- add new option devel_ecdsa for ARM_ROTPK_L
Add support for TBBR using ECDSA keys in ARM platforms
- fixed compile error when KEY_ALG=ecdsa
- add new option ecdsa for TF_MBEDTLS_KEY_ALG
- add new option devel_ecdsa for ARM_ROTPK_LOCATION
- add ecdsa key at plat/arm/board/common/rotpk/
- reduce the mbedtls heap memory size to 13k
Change-Id: I3f7a6170af93fdbaaa7bf2fffb4680a9f6113c13
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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| ddfd38e8 | 24-Aug-2017 |
Qixiang Xu <qixiang.xu@arm.com> |
plat/arm : update BL size macros to give BL1 and BL2 more space for TBB
For Trusted Board Boot, BL1 RW section and BL2 need more space to
support the ECDSA algorithm. Specifically, PLAT_ARM_MAX_BL1_
plat/arm : update BL size macros to give BL1 and BL2 more space for TBB
For Trusted Board Boot, BL1 RW section and BL2 need more space to
support the ECDSA algorithm. Specifically, PLAT_ARM_MAX_BL1_RW_SIZE
is increased on ARM platforms.
And on the Juno platform:
- BL2 size, PLAT_ARM_MAX_BL2_SIZE is increased.
- SCP_BL2 is loaded into the space defined by BL31_BASE ->
BL31_RW_BASE. In order to maintain the same size space for
SCP_BL2,PLAT_ARM_MAX_BL31_SIZE is increased.
Change-Id: I379083f918b40ab1c765da4e71780d89f0058040
Co-Authored-By: David Cunado <david.cunado@arm.com>
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
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