1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <gicv3.h> 12 #include "gicv3_private.h" 13 14 const gicv3_driver_data_t *gicv3_driver_data; 15 static unsigned int gicv2_compat; 16 17 /* 18 * Redistributor power operations are weakly bound so that they can be 19 * overridden 20 */ 21 #pragma weak gicv3_rdistif_off 22 #pragma weak gicv3_rdistif_on 23 24 25 /* Helper macros to save and restore GICD registers to and from the context */ 26 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 27 do { \ 28 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 29 int_id += (1 << REG##_SHIFT)) { \ 30 gicd_write_##reg(base, int_id, \ 31 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT]); \ 32 } \ 33 } while (0) 34 35 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 36 do { \ 37 for (unsigned int int_id = MIN_SPI_ID; int_id < intr_num; \ 38 int_id += (1 << REG##_SHIFT)) { \ 39 ctx->gicd_##reg[(int_id - MIN_SPI_ID) >> REG##_SHIFT] =\ 40 gicd_read_##reg(base, int_id); \ 41 } \ 42 } while (0) 43 44 45 /******************************************************************************* 46 * This function initialises the ARM GICv3 driver in EL3 with provided platform 47 * inputs. 48 ******************************************************************************/ 49 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 50 { 51 unsigned int gic_version; 52 53 assert(plat_driver_data); 54 assert(plat_driver_data->gicd_base); 55 assert(plat_driver_data->gicr_base); 56 assert(plat_driver_data->rdistif_num); 57 assert(plat_driver_data->rdistif_base_addrs); 58 59 assert(IS_IN_EL3()); 60 61 /* 62 * The platform should provide a list of at least one type of 63 * interrupts 64 */ 65 assert(plat_driver_data->g0_interrupt_array || 66 plat_driver_data->g1s_interrupt_array); 67 68 /* 69 * If there are no interrupts of a particular type, then the number of 70 * interrupts of that type should be 0 and vice-versa. 71 */ 72 assert(plat_driver_data->g0_interrupt_array ? 73 plat_driver_data->g0_interrupt_num : 74 plat_driver_data->g0_interrupt_num == 0); 75 assert(plat_driver_data->g1s_interrupt_array ? 76 plat_driver_data->g1s_interrupt_num : 77 plat_driver_data->g1s_interrupt_num == 0); 78 79 /* Check for system register support */ 80 #ifdef AARCH32 81 assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); 82 #else 83 assert(read_id_aa64pfr0_el1() & 84 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); 85 #endif /* AARCH32 */ 86 87 /* The GIC version should be 3.0 */ 88 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 89 gic_version >>= PIDR2_ARCH_REV_SHIFT; 90 gic_version &= PIDR2_ARCH_REV_MASK; 91 assert(gic_version == ARCH_REV_GICV3); 92 93 /* 94 * Find out whether the GIC supports the GICv2 compatibility mode. The 95 * ARE_S bit resets to 0 if supported 96 */ 97 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 98 gicv2_compat >>= CTLR_ARE_S_SHIFT; 99 gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); 100 101 /* 102 * Find the base address of each implemented Redistributor interface. 103 * The number of interfaces should be equal to the number of CPUs in the 104 * system. The memory for saving these addresses has to be allocated by 105 * the platform port 106 */ 107 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 108 plat_driver_data->rdistif_num, 109 plat_driver_data->gicr_base, 110 plat_driver_data->mpidr_to_core_pos); 111 112 gicv3_driver_data = plat_driver_data; 113 114 /* 115 * The GIC driver data is initialized by the primary CPU with caches 116 * enabled. When the secondary CPU boots up, it initializes the 117 * GICC/GICR interface with the caches disabled. Hence flush the 118 * driver data to ensure coherency. This is not required if the 119 * platform has HW_ASSISTED_COHERENCY enabled. 120 */ 121 #if !HW_ASSISTED_COHERENCY 122 flush_dcache_range((uintptr_t) &gicv3_driver_data, 123 sizeof(gicv3_driver_data)); 124 flush_dcache_range((uintptr_t) gicv3_driver_data, 125 sizeof(*gicv3_driver_data)); 126 #endif 127 128 INFO("GICv3 %s legacy support detected." 129 " ARM GICV3 driver initialized in EL3\n", 130 gicv2_compat ? "with" : "without"); 131 } 132 133 /******************************************************************************* 134 * This function initialises the GIC distributor interface based upon the data 135 * provided by the platform while initialising the driver. 136 ******************************************************************************/ 137 void gicv3_distif_init(void) 138 { 139 unsigned int bitmap = 0; 140 141 assert(gicv3_driver_data); 142 assert(gicv3_driver_data->gicd_base); 143 assert(gicv3_driver_data->g1s_interrupt_array || 144 gicv3_driver_data->g0_interrupt_array); 145 146 assert(IS_IN_EL3()); 147 148 /* 149 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 150 * the ARE_S bit. The Distributor might generate a system error 151 * otherwise. 152 */ 153 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 154 CTLR_ENABLE_G0_BIT | 155 CTLR_ENABLE_G1S_BIT | 156 CTLR_ENABLE_G1NS_BIT, 157 RWP_TRUE); 158 159 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 160 gicd_set_ctlr(gicv3_driver_data->gicd_base, 161 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 162 163 /* Set the default attribute of all SPIs */ 164 gicv3_spis_configure_defaults(gicv3_driver_data->gicd_base); 165 166 /* Configure the G1S SPIs */ 167 if (gicv3_driver_data->g1s_interrupt_array) { 168 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base, 169 gicv3_driver_data->g1s_interrupt_num, 170 gicv3_driver_data->g1s_interrupt_array, 171 INTR_GROUP1S); 172 bitmap |= CTLR_ENABLE_G1S_BIT; 173 } 174 175 /* Configure the G0 SPIs */ 176 if (gicv3_driver_data->g0_interrupt_array) { 177 gicv3_secure_spis_configure(gicv3_driver_data->gicd_base, 178 gicv3_driver_data->g0_interrupt_num, 179 gicv3_driver_data->g0_interrupt_array, 180 INTR_GROUP0); 181 bitmap |= CTLR_ENABLE_G0_BIT; 182 } 183 184 /* Enable the secure SPIs now that they have been configured */ 185 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 186 } 187 188 /******************************************************************************* 189 * This function initialises the GIC Redistributor interface of the calling CPU 190 * (identified by the 'proc_num' parameter) based upon the data provided by the 191 * platform while initialising the driver. 192 ******************************************************************************/ 193 void gicv3_rdistif_init(unsigned int proc_num) 194 { 195 uintptr_t gicr_base; 196 197 assert(gicv3_driver_data); 198 assert(proc_num < gicv3_driver_data->rdistif_num); 199 assert(gicv3_driver_data->rdistif_base_addrs); 200 assert(gicv3_driver_data->gicd_base); 201 assert(gicd_read_ctlr(gicv3_driver_data->gicd_base) & CTLR_ARE_S_BIT); 202 assert(gicv3_driver_data->g1s_interrupt_array || 203 gicv3_driver_data->g0_interrupt_array); 204 205 assert(IS_IN_EL3()); 206 207 /* Power on redistributor */ 208 gicv3_rdistif_on(proc_num); 209 210 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 211 212 /* Set the default attribute of all SGIs and PPIs */ 213 gicv3_ppi_sgi_configure_defaults(gicr_base); 214 215 /* Configure the G1S SGIs/PPIs */ 216 if (gicv3_driver_data->g1s_interrupt_array) { 217 gicv3_secure_ppi_sgi_configure(gicr_base, 218 gicv3_driver_data->g1s_interrupt_num, 219 gicv3_driver_data->g1s_interrupt_array, 220 INTR_GROUP1S); 221 } 222 223 /* Configure the G0 SGIs/PPIs */ 224 if (gicv3_driver_data->g0_interrupt_array) { 225 gicv3_secure_ppi_sgi_configure(gicr_base, 226 gicv3_driver_data->g0_interrupt_num, 227 gicv3_driver_data->g0_interrupt_array, 228 INTR_GROUP0); 229 } 230 } 231 232 /******************************************************************************* 233 * Functions to perform power operations on GIC Redistributor 234 ******************************************************************************/ 235 void gicv3_rdistif_off(unsigned int proc_num) 236 { 237 return; 238 } 239 240 void gicv3_rdistif_on(unsigned int proc_num) 241 { 242 return; 243 } 244 245 /******************************************************************************* 246 * This function enables the GIC CPU interface of the calling CPU using only 247 * system register accesses. 248 ******************************************************************************/ 249 void gicv3_cpuif_enable(unsigned int proc_num) 250 { 251 uintptr_t gicr_base; 252 unsigned int scr_el3; 253 unsigned int icc_sre_el3; 254 255 assert(gicv3_driver_data); 256 assert(proc_num < gicv3_driver_data->rdistif_num); 257 assert(gicv3_driver_data->rdistif_base_addrs); 258 assert(IS_IN_EL3()); 259 260 /* Mark the connected core as awake */ 261 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 262 gicv3_rdistif_mark_core_awake(gicr_base); 263 264 /* Disable the legacy interrupt bypass */ 265 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 266 267 /* 268 * Enable system register access for EL3 and allow lower exception 269 * levels to configure the same for themselves. If the legacy mode is 270 * not supported, the SRE bit is RAO/WI 271 */ 272 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 273 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 274 275 scr_el3 = read_scr_el3(); 276 277 /* 278 * Switch to NS state to write Non secure ICC_SRE_EL1 and 279 * ICC_SRE_EL2 registers. 280 */ 281 write_scr_el3(scr_el3 | SCR_NS_BIT); 282 isb(); 283 284 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 285 write_icc_sre_el1(ICC_SRE_SRE_BIT); 286 isb(); 287 288 /* Switch to secure state. */ 289 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 290 isb(); 291 292 /* Program the idle priority in the PMR */ 293 write_icc_pmr_el1(GIC_PRI_MASK); 294 295 /* Enable Group0 interrupts */ 296 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 297 298 /* Enable Group1 Secure interrupts */ 299 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 300 IGRPEN1_EL3_ENABLE_G1S_BIT); 301 302 /* Write the secure ICC_SRE_EL1 register */ 303 write_icc_sre_el1(ICC_SRE_SRE_BIT); 304 isb(); 305 } 306 307 /******************************************************************************* 308 * This function disables the GIC CPU interface of the calling CPU using 309 * only system register accesses. 310 ******************************************************************************/ 311 void gicv3_cpuif_disable(unsigned int proc_num) 312 { 313 uintptr_t gicr_base; 314 315 assert(gicv3_driver_data); 316 assert(proc_num < gicv3_driver_data->rdistif_num); 317 assert(gicv3_driver_data->rdistif_base_addrs); 318 319 assert(IS_IN_EL3()); 320 321 /* Disable legacy interrupt bypass */ 322 write_icc_sre_el3(read_icc_sre_el3() | 323 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 324 325 /* Disable Group0 interrupts */ 326 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 327 ~IGRPEN1_EL1_ENABLE_G0_BIT); 328 329 /* Disable Group1 Secure and Non-Secure interrupts */ 330 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 331 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 332 IGRPEN1_EL3_ENABLE_G1S_BIT)); 333 334 /* Synchronise accesses to group enable registers */ 335 isb(); 336 337 /* Mark the connected core as asleep */ 338 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 339 gicv3_rdistif_mark_core_asleep(gicr_base); 340 } 341 342 /******************************************************************************* 343 * This function returns the id of the highest priority pending interrupt at 344 * the GIC cpu interface. 345 ******************************************************************************/ 346 unsigned int gicv3_get_pending_interrupt_id(void) 347 { 348 unsigned int id; 349 350 assert(IS_IN_EL3()); 351 id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 352 353 /* 354 * If the ID is special identifier corresponding to G1S or G1NS 355 * interrupt, then read the highest pending group 1 interrupt. 356 */ 357 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) 358 return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 359 360 return id; 361 } 362 363 /******************************************************************************* 364 * This function returns the type of the highest priority pending interrupt at 365 * the GIC cpu interface. The return values can be one of the following : 366 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 367 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 368 * 0 - 1019 : The interrupt type is secure Group 0. 369 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 370 * sufficient priority to be signaled 371 ******************************************************************************/ 372 unsigned int gicv3_get_pending_interrupt_type(void) 373 { 374 assert(IS_IN_EL3()); 375 return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 376 } 377 378 /******************************************************************************* 379 * This function returns the type of the interrupt id depending upon the group 380 * this interrupt has been configured under by the interrupt controller i.e. 381 * group0 or group1 Secure / Non Secure. The return value can be one of the 382 * following : 383 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 384 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 385 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 386 * interrupt. 387 ******************************************************************************/ 388 unsigned int gicv3_get_interrupt_type(unsigned int id, 389 unsigned int proc_num) 390 { 391 unsigned int igroup, grpmodr; 392 uintptr_t gicr_base; 393 394 assert(IS_IN_EL3()); 395 assert(gicv3_driver_data); 396 397 /* Ensure the parameters are valid */ 398 assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); 399 assert(proc_num < gicv3_driver_data->rdistif_num); 400 401 /* All LPI interrupts are Group 1 non secure */ 402 if (id >= MIN_LPI_ID) 403 return INTR_GROUP1NS; 404 405 if (id < MIN_SPI_ID) { 406 assert(gicv3_driver_data->rdistif_base_addrs); 407 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 408 igroup = gicr_get_igroupr0(gicr_base, id); 409 grpmodr = gicr_get_igrpmodr0(gicr_base, id); 410 } else { 411 assert(gicv3_driver_data->gicd_base); 412 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 413 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 414 } 415 416 /* 417 * If the IGROUP bit is set, then it is a Group 1 Non secure 418 * interrupt 419 */ 420 if (igroup) 421 return INTR_GROUP1NS; 422 423 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 424 if (grpmodr) 425 return INTR_GROUP1S; 426 427 /* Else it is a Group 0 Secure interrupt */ 428 return INTR_GROUP0; 429 } 430 431 /***************************************************************************** 432 * Function to save the GIC Redistributor register context. This function 433 * must be invoked after CPU interface disable and prior to Distributor save. 434 *****************************************************************************/ 435 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx) 436 { 437 uintptr_t gicr_base; 438 unsigned int int_id; 439 440 assert(gicv3_driver_data); 441 assert(proc_num < gicv3_driver_data->rdistif_num); 442 assert(gicv3_driver_data->rdistif_base_addrs); 443 assert(IS_IN_EL3()); 444 assert(rdist_ctx); 445 446 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 447 448 /* 449 * Wait for any write to GICR_CTLR to complete before trying to save any 450 * state. 451 */ 452 gicr_wait_for_pending_write(gicr_base); 453 454 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 455 456 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 457 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 458 459 rdist_ctx->gicr_igroupr0 = gicr_read_igroupr0(gicr_base); 460 rdist_ctx->gicr_isenabler0 = gicr_read_isenabler0(gicr_base); 461 rdist_ctx->gicr_ispendr0 = gicr_read_ispendr0(gicr_base); 462 rdist_ctx->gicr_isactiver0 = gicr_read_isactiver0(gicr_base); 463 rdist_ctx->gicr_icfgr0 = gicr_read_icfgr0(gicr_base); 464 rdist_ctx->gicr_icfgr1 = gicr_read_icfgr1(gicr_base); 465 rdist_ctx->gicr_igrpmodr0 = gicr_read_igrpmodr0(gicr_base); 466 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 467 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 468 int_id += (1 << IPRIORITYR_SHIFT)) { 469 rdist_ctx->gicr_ipriorityr[(int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT] = 470 gicr_read_ipriorityr(gicr_base, int_id); 471 } 472 473 474 /* 475 * Call the pre-save hook that implements the IMP DEF sequence that may 476 * be required on some GIC implementations. As this may need to access 477 * the Redistributor registers, we pass it proc_num. 478 */ 479 gicv3_distif_pre_save(proc_num); 480 } 481 482 /***************************************************************************** 483 * Function to restore the GIC Redistributor register context. We disable 484 * LPI and per-cpu interrupts before we start restore of the Redistributor. 485 * This function must be invoked after Distributor restore but prior to 486 * CPU interface enable. The pending and active interrupts are restored 487 * after the interrupts are fully configured and enabled. 488 *****************************************************************************/ 489 void gicv3_rdistif_init_restore(unsigned int proc_num, 490 const gicv3_redist_ctx_t * const rdist_ctx) 491 { 492 uintptr_t gicr_base; 493 unsigned int int_id; 494 495 assert(gicv3_driver_data); 496 assert(proc_num < gicv3_driver_data->rdistif_num); 497 assert(gicv3_driver_data->rdistif_base_addrs); 498 assert(IS_IN_EL3()); 499 assert(rdist_ctx); 500 501 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 502 503 /* Power on redistributor */ 504 gicv3_rdistif_on(proc_num); 505 506 /* 507 * Call the post-restore hook that implements the IMP DEF sequence that 508 * may be required on some GIC implementations. As this may need to 509 * access the Redistributor registers, we pass it proc_num. 510 */ 511 gicv3_distif_post_restore(proc_num); 512 513 /* 514 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a 515 * more scalable approach as it avoids clearing the enable bits in the 516 * GICD_CTLR 517 */ 518 gicr_write_icenabler0(gicr_base, ~0); 519 /* Wait for pending writes to GICR_ICENABLER */ 520 gicr_wait_for_pending_write(gicr_base); 521 522 /* 523 * Disable the LPIs to avoid unpredictable behavior when writing to 524 * GICR_PROPBASER and GICR_PENDBASER. 525 */ 526 gicr_write_ctlr(gicr_base, 527 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 528 529 /* Restore registers' content */ 530 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 531 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 532 533 gicr_write_igroupr0(gicr_base, rdist_ctx->gicr_igroupr0); 534 535 for (int_id = MIN_SGI_ID; int_id < TOTAL_PCPU_INTR_NUM; 536 int_id += (1 << IPRIORITYR_SHIFT)) { 537 gicr_write_ipriorityr(gicr_base, int_id, 538 rdist_ctx->gicr_ipriorityr[ 539 (int_id - MIN_SGI_ID) >> IPRIORITYR_SHIFT]); 540 } 541 542 gicr_write_icfgr0(gicr_base, rdist_ctx->gicr_icfgr0); 543 gicr_write_icfgr1(gicr_base, rdist_ctx->gicr_icfgr1); 544 gicr_write_igrpmodr0(gicr_base, rdist_ctx->gicr_igrpmodr0); 545 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 546 547 /* Restore after group and priorities are set */ 548 gicr_write_ispendr0(gicr_base, rdist_ctx->gicr_ispendr0); 549 gicr_write_isactiver0(gicr_base, rdist_ctx->gicr_isactiver0); 550 551 /* 552 * Wait for all writes to the Distributor to complete before enabling 553 * the SGI and PPIs. 554 */ 555 gicr_wait_for_upstream_pending_write(gicr_base); 556 gicr_write_isenabler0(gicr_base, rdist_ctx->gicr_isenabler0); 557 558 /* 559 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 560 * the first write to GICR_CTLR was still in flight (this write only 561 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 562 * bit). 563 */ 564 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 565 gicr_wait_for_pending_write(gicr_base); 566 } 567 568 /***************************************************************************** 569 * Function to save the GIC Distributor register context. This function 570 * must be invoked after CPU interface disable and Redistributor save. 571 *****************************************************************************/ 572 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 573 { 574 unsigned int num_ints; 575 576 assert(gicv3_driver_data); 577 assert(gicv3_driver_data->gicd_base); 578 assert(IS_IN_EL3()); 579 assert(dist_ctx); 580 581 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 582 583 num_ints = gicd_read_typer(gicd_base); 584 num_ints &= TYPER_IT_LINES_NO_MASK; 585 num_ints = (num_ints + 1) << 5; 586 587 assert(num_ints <= MAX_SPI_ID + 1); 588 589 /* Wait for pending write to complete */ 590 gicd_wait_for_pending_write(gicd_base); 591 592 /* Save the GICD_CTLR */ 593 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 594 595 /* Save GICD_IGROUPR for INTIDs 32 - 1020 */ 596 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 597 598 /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */ 599 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 600 601 /* Save GICD_ISPENDR for INTIDs 32 - 1020 */ 602 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 603 604 /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */ 605 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 606 607 /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */ 608 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 609 610 /* Save GICD_ICFGR for INTIDs 32 - 1020 */ 611 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 612 613 /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */ 614 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 615 616 /* Save GICD_NSACR for INTIDs 32 - 1020 */ 617 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 618 619 /* Save GICD_IROUTER for INTIDs 32 - 1024 */ 620 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 621 622 /* 623 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 624 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 625 * driver. 626 */ 627 } 628 629 /***************************************************************************** 630 * Function to restore the GIC Distributor register context. We disable G0, G1S 631 * and G1NS interrupt groups before we start restore of the Distributor. This 632 * function must be invoked prior to Redistributor restore and CPU interface 633 * enable. The pending and active interrupts are restored after the interrupts 634 * are fully configured and enabled. 635 *****************************************************************************/ 636 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 637 { 638 unsigned int num_ints = 0; 639 640 assert(gicv3_driver_data); 641 assert(gicv3_driver_data->gicd_base); 642 assert(IS_IN_EL3()); 643 assert(dist_ctx); 644 645 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 646 647 /* 648 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 649 * the ARE_S bit. The Distributor might generate a system error 650 * otherwise. 651 */ 652 gicd_clr_ctlr(gicd_base, 653 CTLR_ENABLE_G0_BIT | 654 CTLR_ENABLE_G1S_BIT | 655 CTLR_ENABLE_G1NS_BIT, 656 RWP_TRUE); 657 658 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 659 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 660 661 num_ints = gicd_read_typer(gicd_base); 662 num_ints &= TYPER_IT_LINES_NO_MASK; 663 num_ints = (num_ints + 1) << 5; 664 665 assert(num_ints <= MAX_SPI_ID + 1); 666 667 /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */ 668 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR); 669 670 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */ 671 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR); 672 673 /* Restore GICD_ICFGR for INTIDs 32 - 1020 */ 674 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR); 675 676 /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */ 677 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR); 678 679 /* Restore GICD_NSACR for INTIDs 32 - 1020 */ 680 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR); 681 682 /* Restore GICD_IROUTER for INTIDs 32 - 1020 */ 683 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER); 684 685 /* 686 * Restore ISENABLER, ISPENDR and ISACTIVER after the interrupts are 687 * configured. 688 */ 689 690 /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */ 691 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER); 692 693 /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */ 694 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR); 695 696 /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */ 697 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER); 698 699 /* Restore the GICD_CTLR */ 700 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 701 gicd_wait_for_pending_write(gicd_base); 702 703 } 704