1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __ARM_DEF_H__ 7 #define __ARM_DEF_H__ 8 9 #include <arch.h> 10 #include <common_def.h> 11 #include <platform_def.h> 12 #include <tbbr_img_def.h> 13 #include <utils_def.h> 14 #include <xlat_tables_defs.h> 15 16 17 /****************************************************************************** 18 * Definitions common to all ARM standard platforms 19 *****************************************************************************/ 20 21 /* Special value used to verify platform parameters from BL2 to BL31 */ 22 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 23 24 #define ARM_SYSTEM_COUNT 1 25 26 #define ARM_CACHE_WRITEBACK_SHIFT 6 27 28 /* 29 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 30 * power levels have a 1:1 mapping with the MPIDR affinity levels. 31 */ 32 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 33 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 34 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 35 36 /* 37 * Macros for local power states in ARM platforms encoded by State-ID field 38 * within the power-state parameter. 39 */ 40 /* Local power state for power domains in Run state. */ 41 #define ARM_LOCAL_STATE_RUN 0 42 /* Local power state for retention. Valid only for CPU power domains */ 43 #define ARM_LOCAL_STATE_RET 1 44 /* Local power state for OFF/power-down. Valid for CPU and cluster power 45 domains */ 46 #define ARM_LOCAL_STATE_OFF 2 47 48 /* Memory location options for TSP */ 49 #define ARM_TRUSTED_SRAM_ID 0 50 #define ARM_TRUSTED_DRAM_ID 1 51 #define ARM_DRAM_ID 2 52 53 /* The first 4KB of Trusted SRAM are used as shared memory */ 54 #define ARM_TRUSTED_SRAM_BASE 0x04000000 55 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 56 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 57 58 /* The remaining Trusted SRAM is used to load the BL images */ 59 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 60 ARM_SHARED_RAM_SIZE) 61 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 62 ARM_SHARED_RAM_SIZE) 63 64 /* 65 * The top 16MB of DRAM1 is configured as secure access only using the TZC 66 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 67 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 68 */ 69 #define ARM_TZC_DRAM1_SIZE ULL(0x01000000) 70 71 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 72 ARM_DRAM1_SIZE - \ 73 ARM_SCP_TZC_DRAM1_SIZE) 74 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 75 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 76 ARM_SCP_TZC_DRAM1_SIZE - 1) 77 78 /* 79 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 80 * firmware. This region is meant to be NOLOAD and will not be zero 81 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 82 * placed here. 83 */ 84 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) 85 #define ARM_EL3_TZC_DRAM1_SIZE ULL(0x00200000) /* 2 MB */ 86 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 87 ARM_EL3_TZC_DRAM1_SIZE - 1) 88 89 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 90 ARM_DRAM1_SIZE - \ 91 ARM_TZC_DRAM1_SIZE) 92 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 93 (ARM_SCP_TZC_DRAM1_SIZE + \ 94 ARM_EL3_TZC_DRAM1_SIZE)) 95 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 96 ARM_AP_TZC_DRAM1_SIZE - 1) 97 98 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 99 #if ARM_CRYPTOCELL_INTEG 100 /* 101 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 102 * This is required by CryptoCell to authenticate BL33 which is loaded 103 * into the Non Secure DDR. 104 */ 105 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 106 #else 107 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 108 #endif 109 110 #ifdef SPD_opteed 111 /* 112 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 113 * load/authenticate the trusted os extra image. The first 512KB of 114 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 115 * for OPTEE is paged image which only include the paging part using 116 * virtual memory but without "init" data. OPTEE will copy the "init" data 117 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 118 * extra image behind the "init" data. 119 */ 120 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 121 ARM_AP_TZC_DRAM1_SIZE - \ 122 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 123 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 124 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 125 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 126 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 127 MT_MEMORY | MT_RW | MT_SECURE) 128 129 /* 130 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 131 * support is enabled). 132 */ 133 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 134 BL32_BASE, \ 135 BL32_LIMIT - BL32_BASE, \ 136 MT_MEMORY | MT_RW | MT_SECURE) 137 #endif /* SPD_opteed */ 138 139 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 140 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 141 ARM_TZC_DRAM1_SIZE) 142 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 143 ARM_NS_DRAM1_SIZE - 1) 144 145 #define ARM_DRAM1_BASE ULL(0x80000000) 146 #define ARM_DRAM1_SIZE ULL(0x80000000) 147 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 148 ARM_DRAM1_SIZE - 1) 149 150 #define ARM_DRAM2_BASE ULL(0x880000000) 151 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 152 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 153 ARM_DRAM2_SIZE - 1) 154 155 #define ARM_IRQ_SEC_PHY_TIMER 29 156 157 #define ARM_IRQ_SEC_SGI_0 8 158 #define ARM_IRQ_SEC_SGI_1 9 159 #define ARM_IRQ_SEC_SGI_2 10 160 #define ARM_IRQ_SEC_SGI_3 11 161 #define ARM_IRQ_SEC_SGI_4 12 162 #define ARM_IRQ_SEC_SGI_5 13 163 #define ARM_IRQ_SEC_SGI_6 14 164 #define ARM_IRQ_SEC_SGI_7 15 165 166 /* 167 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 168 * terminology. On a GICv2 system or mode, the lists will be merged and treated 169 * as Group 0 interrupts. 170 */ 171 #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 172 ARM_IRQ_SEC_SGI_1, \ 173 ARM_IRQ_SEC_SGI_2, \ 174 ARM_IRQ_SEC_SGI_3, \ 175 ARM_IRQ_SEC_SGI_4, \ 176 ARM_IRQ_SEC_SGI_5, \ 177 ARM_IRQ_SEC_SGI_7 178 179 #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ 180 ARM_IRQ_SEC_SGI_6 181 182 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 183 ARM_SHARED_RAM_BASE, \ 184 ARM_SHARED_RAM_SIZE, \ 185 MT_DEVICE | MT_RW | MT_SECURE) 186 187 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 188 ARM_NS_DRAM1_BASE, \ 189 ARM_NS_DRAM1_SIZE, \ 190 MT_MEMORY | MT_RW | MT_NS) 191 192 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 193 ARM_DRAM2_BASE, \ 194 ARM_DRAM2_SIZE, \ 195 MT_MEMORY | MT_RW | MT_NS) 196 #ifdef SPD_tspd 197 198 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 199 TSP_SEC_MEM_BASE, \ 200 TSP_SEC_MEM_SIZE, \ 201 MT_MEMORY | MT_RW | MT_SECURE) 202 #endif 203 204 #if ARM_BL31_IN_DRAM 205 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 206 BL31_BASE, \ 207 PLAT_ARM_MAX_BL31_SIZE, \ 208 MT_MEMORY | MT_RW | MT_SECURE) 209 #endif 210 211 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 212 ARM_EL3_TZC_DRAM1_BASE, \ 213 ARM_EL3_TZC_DRAM1_SIZE, \ 214 MT_MEMORY | MT_RW | MT_SECURE) 215 216 /* 217 * The number of regions like RO(code), coherent and data required by 218 * different BL stages which need to be mapped in the MMU. 219 */ 220 #if USE_COHERENT_MEM 221 #define ARM_BL_REGIONS 3 222 #else 223 #define ARM_BL_REGIONS 2 224 #endif 225 226 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 227 ARM_BL_REGIONS) 228 229 /* Memory mapped Generic timer interfaces */ 230 #define ARM_SYS_CNTCTL_BASE 0x2a430000 231 #define ARM_SYS_CNTREAD_BASE 0x2a800000 232 #define ARM_SYS_TIMCTL_BASE 0x2a810000 233 234 #define ARM_CONSOLE_BAUDRATE 115200 235 236 /* Trusted Watchdog constants */ 237 #define ARM_SP805_TWDG_BASE 0x2a490000 238 #define ARM_SP805_TWDG_CLK_HZ 32768 239 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 240 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 241 #define ARM_TWDG_TIMEOUT_SEC 128 242 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 243 ARM_TWDG_TIMEOUT_SEC) 244 245 /****************************************************************************** 246 * Required platform porting definitions common to all ARM standard platforms 247 *****************************************************************************/ 248 249 /* 250 * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for 251 * AArch64 builds 252 */ 253 #ifdef AARCH64 254 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36) 255 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36) 256 #else 257 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 258 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 259 #endif 260 261 262 /* 263 * This macro defines the deepest retention state possible. A higher state 264 * id will represent an invalid or a power down state. 265 */ 266 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 267 268 /* 269 * This macro defines the deepest power down states possible. Any state ID 270 * higher than this is invalid. 271 */ 272 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 273 274 /* 275 * Some data must be aligned on the biggest cache line size in the platform. 276 * This is known only to the platform as it might have a combination of 277 * integrated and external caches. 278 */ 279 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 280 281 282 /******************************************************************************* 283 * BL1 specific defines. 284 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 285 * addresses. 286 ******************************************************************************/ 287 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 288 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 289 + PLAT_ARM_TRUSTED_ROM_SIZE) 290 /* 291 * Put BL1 RW at the top of the Trusted SRAM. 292 */ 293 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 294 ARM_BL_RAM_SIZE - \ 295 PLAT_ARM_MAX_BL1_RW_SIZE) 296 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 297 298 /******************************************************************************* 299 * BL2 specific defines. 300 ******************************************************************************/ 301 #if ARM_BL31_IN_DRAM || (defined(AARCH32) && !defined(JUNO_AARCH32_EL3_RUNTIME)) 302 /* 303 * For AArch32 BL31 is not applicable. 304 * For AArch64 BL31 is loaded in the DRAM. 305 * Put BL2 just below BL1. 306 */ 307 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 308 #define BL2_LIMIT BL1_RW_BASE 309 #else 310 /* 311 * Put BL2 just below BL31. 312 */ 313 #define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) 314 #define BL2_LIMIT BL31_BASE 315 #endif 316 317 /******************************************************************************* 318 * BL31 specific defines. 319 ******************************************************************************/ 320 #if ARM_BL31_IN_DRAM 321 /* 322 * Put BL31 at the bottom of TZC secured DRAM 323 */ 324 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 325 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 326 PLAT_ARM_MAX_BL31_SIZE) 327 #elif (RESET_TO_BL31) 328 /* 329 * Put BL31_BASE in the middle of the Trusted SRAM. 330 */ 331 #define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \ 332 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1)) 333 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 334 #else 335 /* 336 * Put BL31 at the top of the Trusted SRAM. 337 */ 338 #define BL31_BASE (ARM_BL_RAM_BASE + \ 339 ARM_BL_RAM_SIZE - \ 340 PLAT_ARM_MAX_BL31_SIZE) 341 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 342 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 343 #endif 344 345 /******************************************************************************* 346 * BL32 specific defines. 347 ******************************************************************************/ 348 /* 349 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 350 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 351 * controller. 352 */ 353 #if ARM_BL31_IN_DRAM 354 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 355 PLAT_ARM_MAX_BL31_SIZE) 356 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 357 PLAT_ARM_MAX_BL31_SIZE) 358 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 359 PLAT_ARM_MAX_BL31_SIZE) 360 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 361 ARM_AP_TZC_DRAM1_SIZE) 362 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 363 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 364 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 365 # define TSP_PROGBITS_LIMIT BL2_BASE 366 # define BL32_BASE ARM_BL_RAM_BASE 367 # define BL32_LIMIT BL31_BASE 368 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 369 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 370 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 371 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 372 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 373 + (1 << 21)) 374 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 375 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 376 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 377 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 378 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 379 ARM_AP_TZC_DRAM1_SIZE) 380 #else 381 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 382 #endif 383 384 /* BL32 is mandatory in AArch32 */ 385 #ifndef AARCH32 386 #ifdef SPD_none 387 #undef BL32_BASE 388 #endif /* SPD_none */ 389 #endif 390 391 /******************************************************************************* 392 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 393 ******************************************************************************/ 394 #define BL2U_BASE BL2_BASE 395 #if ARM_BL31_IN_DRAM || (defined(AARCH32) && !defined(JUNO_AARCH32_EL3_RUNTIME)) 396 /* 397 * For AArch32 BL31 is not applicable. 398 * For AArch64 BL31 is loaded in the DRAM. 399 * BL2U extends up to BL1. 400 */ 401 #define BL2U_LIMIT BL1_RW_BASE 402 #else 403 /* BL2U extends up to BL31. */ 404 #define BL2U_LIMIT BL31_BASE 405 #endif 406 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 407 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) 408 409 /* 410 * ID of the secure physical generic timer interrupt used by the TSP. 411 */ 412 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 413 414 415 /* 416 * One cache line needed for bakery locks on ARM platforms 417 */ 418 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 419 420 421 #endif /* __ARM_DEF_H__ */ 422