1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <cci.h> 11 #include <ccn.h> 12 #include <debug.h> 13 #include <gicv2.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <v2m_def.h> 17 #include "../fvp_def.h" 18 19 /* Defines for GIC Driver build time selection */ 20 #define FVP_GICV2 1 21 #define FVP_GICV3 2 22 #define FVP_GICV3_LEGACY 3 23 24 /******************************************************************************* 25 * arm_config holds the characteristics of the differences between the three FVP 26 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 27 * at each boot stage by the primary before enabling the MMU (to allow 28 * interconnect configuration) & used thereafter. Each BL will have its own copy 29 * to allow independent operation. 30 ******************************************************************************/ 31 arm_config_t arm_config; 32 33 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 34 DEVICE0_SIZE, \ 35 MT_DEVICE | MT_RW | MT_SECURE) 36 37 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 38 DEVICE1_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 /* 42 * Need to be mapped with write permissions in order to set a new non-volatile 43 * counter value. 44 */ 45 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 46 DEVICE2_SIZE, \ 47 MT_DEVICE | MT_RW | MT_SECURE) 48 49 50 /* 51 * Table of memory regions for various BL stages to map using the MMU. 52 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 53 * takes care of mapping it. 54 * 55 * The flash needs to be mapped as writable in order to erase the FIP's Table of 56 * Contents in case of unrecoverable error (see plat_error_handler()). 57 */ 58 #ifdef IMAGE_BL1 59 const mmap_region_t plat_arm_mmap[] = { 60 ARM_MAP_SHARED_RAM, 61 V2M_MAP_FLASH0_RW, 62 V2M_MAP_IOFPGA, 63 MAP_DEVICE0, 64 MAP_DEVICE1, 65 #if TRUSTED_BOARD_BOOT 66 /* To access the Root of Trust Public Key registers. */ 67 MAP_DEVICE2, 68 /* Map DRAM to authenticate NS_BL2U image. */ 69 ARM_MAP_NS_DRAM1, 70 #endif 71 {0} 72 }; 73 #endif 74 #ifdef IMAGE_BL2 75 const mmap_region_t plat_arm_mmap[] = { 76 ARM_MAP_SHARED_RAM, 77 V2M_MAP_FLASH0_RW, 78 V2M_MAP_IOFPGA, 79 MAP_DEVICE0, 80 MAP_DEVICE1, 81 ARM_MAP_NS_DRAM1, 82 #ifdef SPD_tspd 83 ARM_MAP_TSP_SEC_MEM, 84 #endif 85 #if TRUSTED_BOARD_BOOT 86 /* To access the Root of Trust Public Key registers. */ 87 MAP_DEVICE2, 88 #endif 89 #if ARM_BL31_IN_DRAM 90 ARM_MAP_BL31_SEC_DRAM, 91 #endif 92 #ifdef SPD_opteed 93 ARM_MAP_OPTEE_CORE_MEM, 94 ARM_OPTEE_PAGEABLE_LOAD_MEM, 95 #endif 96 {0} 97 }; 98 #endif 99 #ifdef IMAGE_BL2U 100 const mmap_region_t plat_arm_mmap[] = { 101 MAP_DEVICE0, 102 V2M_MAP_IOFPGA, 103 {0} 104 }; 105 #endif 106 #ifdef IMAGE_BL31 107 const mmap_region_t plat_arm_mmap[] = { 108 ARM_MAP_SHARED_RAM, 109 V2M_MAP_IOFPGA, 110 MAP_DEVICE0, 111 MAP_DEVICE1, 112 ARM_V2M_MAP_MEM_PROTECT, 113 {0} 114 }; 115 #endif 116 #ifdef IMAGE_BL32 117 const mmap_region_t plat_arm_mmap[] = { 118 #ifdef AARCH32 119 ARM_MAP_SHARED_RAM, 120 #endif 121 V2M_MAP_IOFPGA, 122 MAP_DEVICE0, 123 MAP_DEVICE1, 124 {0} 125 }; 126 #endif 127 128 ARM_CASSERT_MMAP 129 130 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 131 static const int fvp_cci400_map[] = { 132 PLAT_FVP_CCI400_CLUS0_SL_PORT, 133 PLAT_FVP_CCI400_CLUS1_SL_PORT, 134 }; 135 136 static const int fvp_cci5xx_map[] = { 137 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 138 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 139 }; 140 141 static unsigned int get_interconnect_master(void) 142 { 143 unsigned int master; 144 u_register_t mpidr; 145 146 mpidr = read_mpidr_el1(); 147 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 148 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 149 150 assert(master < FVP_CLUSTER_COUNT); 151 return master; 152 } 153 #endif 154 155 /******************************************************************************* 156 * A single boot loader stack is expected to work on both the Foundation FVP 157 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 158 * SYS_ID register provides a mechanism for detecting the differences between 159 * these platforms. This information is stored in a per-BL array to allow the 160 * code to take the correct path.Per BL platform configuration. 161 ******************************************************************************/ 162 void fvp_config_setup(void) 163 { 164 unsigned int rev, hbi, bld, arch, sys_id; 165 166 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 167 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 168 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 169 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 170 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 171 172 if (arch != ARCH_MODEL) { 173 ERROR("This firmware is for FVP models\n"); 174 panic(); 175 } 176 177 /* 178 * The build field in the SYS_ID tells which variant of the GIC 179 * memory is implemented by the model. 180 */ 181 switch (bld) { 182 case BLD_GIC_VE_MMAP: 183 ERROR("Legacy Versatile Express memory map for GIC peripheral" 184 " is not supported\n"); 185 panic(); 186 break; 187 case BLD_GIC_A53A57_MMAP: 188 break; 189 default: 190 ERROR("Unsupported board build %x\n", bld); 191 panic(); 192 } 193 194 /* 195 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 196 * for the Foundation FVP. 197 */ 198 switch (hbi) { 199 case HBI_FOUNDATION_FVP: 200 arm_config.flags = 0; 201 202 /* 203 * Check for supported revisions of Foundation FVP 204 * Allow future revisions to run but emit warning diagnostic 205 */ 206 switch (rev) { 207 case REV_FOUNDATION_FVP_V2_0: 208 case REV_FOUNDATION_FVP_V2_1: 209 case REV_FOUNDATION_FVP_v9_1: 210 case REV_FOUNDATION_FVP_v9_6: 211 break; 212 default: 213 WARN("Unrecognized Foundation FVP revision %x\n", rev); 214 break; 215 } 216 break; 217 case HBI_BASE_FVP: 218 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 219 220 /* 221 * Check for supported revisions 222 * Allow future revisions to run but emit warning diagnostic 223 */ 224 switch (rev) { 225 case REV_BASE_FVP_V0: 226 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 227 break; 228 case REV_BASE_FVP_REVC: 229 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 230 ARM_CONFIG_FVP_HAS_CCI5XX); 231 break; 232 default: 233 WARN("Unrecognized Base FVP revision %x\n", rev); 234 break; 235 } 236 break; 237 default: 238 ERROR("Unsupported board HBI number 0x%x\n", hbi); 239 panic(); 240 } 241 242 /* 243 * We assume that the presence of MT bit, and therefore shifted 244 * affinities, is uniform across the platform: either all CPUs, or no 245 * CPUs implement it. 246 */ 247 if (read_mpidr_el1() & MPIDR_MT_MASK) 248 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 249 } 250 251 252 void fvp_interconnect_init(void) 253 { 254 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 255 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 256 ERROR("Unrecognized CCN variant detected. Only CCN-502" 257 " is supported"); 258 panic(); 259 } 260 261 plat_arm_interconnect_init(); 262 #else 263 uintptr_t cci_base = 0; 264 const int *cci_map = 0; 265 unsigned int map_size = 0; 266 267 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 268 ARM_CONFIG_FVP_HAS_CCI5XX))) { 269 return; 270 } 271 272 /* Initialize the right interconnect */ 273 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 274 cci_base = PLAT_FVP_CCI5XX_BASE; 275 cci_map = fvp_cci5xx_map; 276 map_size = ARRAY_SIZE(fvp_cci5xx_map); 277 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 278 cci_base = PLAT_FVP_CCI400_BASE; 279 cci_map = fvp_cci400_map; 280 map_size = ARRAY_SIZE(fvp_cci400_map); 281 } 282 283 assert(cci_base); 284 assert(cci_map); 285 cci_init(cci_base, cci_map, map_size); 286 #endif 287 } 288 289 void fvp_interconnect_enable(void) 290 { 291 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 292 plat_arm_interconnect_enter_coherency(); 293 #else 294 unsigned int master; 295 296 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 297 ARM_CONFIG_FVP_HAS_CCI5XX)) { 298 master = get_interconnect_master(); 299 cci_enable_snoop_dvm_reqs(master); 300 } 301 #endif 302 } 303 304 void fvp_interconnect_disable(void) 305 { 306 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 307 plat_arm_interconnect_exit_coherency(); 308 #else 309 unsigned int master; 310 311 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 312 ARM_CONFIG_FVP_HAS_CCI5XX)) { 313 master = get_interconnect_master(); 314 cci_disable_snoop_dvm_reqs(master); 315 } 316 #endif 317 } 318