| f2aa4e88 | 23-Apr-2019 |
Chris Kay <chris.kay@arm.com> |
plat/sgm: Always use SCMI for SGM platforms
As on SGI platforms, SCPI is unsupported on SGM platforms.
Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08
Signed-off-by: Chris Kay <chris.kay@arm.c
plat/sgm: Always use SCMI for SGM platforms
As on SGI platforms, SCPI is unsupported on SGM platforms.
Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08
Signed-off-by: Chris Kay <chris.kay@arm.com>
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| 3c6ec8f1 | 22-Jan-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Revert "plat/arm: Add support for SEPARATE_NOBITS_REGION"
This reverts commit d433bbdd459c222e5bf5ca87319807465b246d8c.
Change-Id: I46c69dce704a1ce1b50452dd4d62425c4a67f7f0 |
| d433bbdd | 16-Jan-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
plat/arm: Add support for SEPARATE_NOBITS_REGION
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence m
plat/arm: Add support for SEPARATE_NOBITS_REGION
In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
the build to require that ARM_BL31_IN_DRAM is enabled as well.
Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code
cannot be reclaimed to be used for runtime data such as secondary cpu stacks.
Memory map for BL31 NOBITS region also has to be created.
Change-Id: Ibd480f82c1dc74e9cbb54eec07d7a8fecbf25433
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| 43636796 | 10-Jan-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "Unify type of "cpu_idx" across PSCI module." into integration |
| 5b33ad17 | 13-Dec-2019 |
Deepika Bhavnani <deepika.bhavnani@arm.com> |
Unify type of "cpu_idx" across PSCI module.
NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned i
Unify type of "cpu_idx" across PSCI module.
NOTE for platform integrators:
API `plat_psci_stat_get_residency()` third argument
`last_cpu_idx` is changed from "signed int" to the
"unsigned int" type.
Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.
2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent
Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.
Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required
Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c
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| 5c330967 | 10-Jan-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "FVP: Remove re-definition of topology related build options" into integration |
| 865054dc | 10-Jan-2020 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "FVP: Stop reclaiming init code with Clang builds" into integration |
| 94f1c959 | 10-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
FVP: Remove re-definition of topology related build options
This patch removes re-definition of the following FVP build
options from plat\arm\board\fvp\fvp_def.h:
'FVP_CLUSTER_COUNT'
'FVP_MAX_CPUS
FVP: Remove re-definition of topology related build options
This patch removes re-definition of the following FVP build
options from plat\arm\board\fvp\fvp_def.h:
'FVP_CLUSTER_COUNT'
'FVP_MAX_CPUS_PER_CLUSTER'
'FVP_MAX_PE_PER_CPU'
which are set in platform.mk.
This fixes a potential problem when a build option set in
platform.mk file can be re-defined in fvp_def.h header file
used by other build component with a different makefile which
does not set this option.
Ref. GENFW-3505.
Change-Id: I4288629920516acf2c239c7b733f92a0c5a812ff
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| 44abf27d | 08-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "A5DS: Change boot address to point to DDR address" into integration |
| 8849298c | 07-Jan-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "A5DS: Correct system freq, Cache Writeback Granule" into integration |
| a6ffd375 | 17-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
FVP: Stop reclaiming init code with Clang builds
The reclaim init code functionality relies on forward reference in the
linker script. The LLVM linker does not process it correctly.
Change-Id: I993
FVP: Stop reclaiming init code with Clang builds
The reclaim init code functionality relies on forward reference in the
linker script. The LLVM linker does not process it correctly.
Change-Id: I993aeb9587bfa07af25b60ed823a6a2c5e970c94
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
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| e343bf13 | 18-Dec-2019 |
Avinash Mehta <avinash.mehta@arm.com> |
A5DS: Change boot address to point to DDR address
Point boot address to DDR location for booting A5DS FPGA
FIP, Kernel and rootfs are sideloaded to DDR
Also move BL2 to higher address in DDR
Change
A5DS: Change boot address to point to DDR address
Point boot address to DDR location for booting A5DS FPGA
FIP, Kernel and rootfs are sideloaded to DDR
Also move BL2 to higher address in DDR
Change-Id: Ia2a57a0bda776a1a0a96bcd3cfb5c6cd2cf4dc04
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
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| 786890ca | 18-Dec-2019 |
Avinash Mehta <avinash.mehta@arm.com> |
A5DS: Correct system freq, Cache Writeback Granule
Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeb
A5DS: Correct system freq, Cache Writeback Granule
Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeback
Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
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| c20c0525 | 13-Dec-2019 |
Vishnu Banavath <vishnu.banavath@arm.com> |
drivers: add a driver for snoop control unit
The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.
The SCU functions are to:
- maintain data c
drivers: add a driver for snoop control unit
The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.
The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
L2 accesses
- manage ACP accesses.
Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.
This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT
Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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| 86ed8953 | 20-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "debugfs: add SMC channel" into integration |
| 962c44e7 | 15-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
spm-mm: Remove mm_svc.h header
The contents of this header have been merged into the spm_mm_svc.h
header file.
Change-Id: I01530b2e4ec1b4c091ce339758025e2216e740a4
Signed-off-by: Paul Beesley <paul
spm-mm: Remove mm_svc.h header
The contents of this header have been merged into the spm_mm_svc.h
header file.
Change-Id: I01530b2e4ec1b4c091ce339758025e2216e740a4
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 0bf9f567 | 15-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
spm-mm: Refactor spm_svc.h and its contents
Change-Id: I91c192924433226b54d33e57d56d146c1c6df81b
Signed-off-by: Paul Beesley <paul.beesley@arm.com> |
| aeaa225c | 15-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
spm-mm: Refactor secure_partition.h and its contents
Before adding any new SPM-related components we should first do
some cleanup around the existing SPM-MM implementation. The aim
is to make sure t
spm-mm: Refactor secure_partition.h and its contents
Before adding any new SPM-related components we should first do
some cleanup around the existing SPM-MM implementation. The aim
is to make sure that any SPM-MM components have names that clearly
indicate that they are MM-related. Otherwise, when adding new SPM
code, it could quickly become confusing as it would be unclear to
which component the code belongs.
The secure_partition.h header is a clear example of this, as the
name is generic so it could easily apply to any SPM-related code,
when it is in fact SPM-MM specific.
This patch renames the file and the two structures defined within
it, and then modifies any references in files that use the header.
Change-Id: I44bd95fab774c358178b3e81262a16da500fda26
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| 538b0020 | 14-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
spm: Remove SPM Alpha 1 prototype and support files
The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component
spm: Remove SPM Alpha 1 prototype and support files
The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component that, in turn, enables partition managers
at S-EL2 / S-EL1.
This patch removes:
- The core service files (std_svc/spm)
- The Resource Descriptor headers (include/services)
- SPRT protocol support and service definitions
- SPCI protocol support and service definitions
Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
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| 3f3c341a | 16-Sep-2019 |
Paul Beesley <paul.beesley@arm.com> |
Remove dependency between SPM_MM and ENABLE_SPM build flags
There are two different implementations of Secure Partition
management in TF-A. One is based on the "Management Mode" (MM)
design, the oth
Remove dependency between SPM_MM and ENABLE_SPM build flags
There are two different implementations of Secure Partition
management in TF-A. One is based on the "Management Mode" (MM)
design, the other is based on the Secure Partition Client Interface
(SPCI) specification. Currently there is a dependency between their
build flags that shouldn't exist, making further development
harder than it should be. This patch removes that
dependency, making the two flags function independently.
Before: ENABLE_SPM=1 is required for using either implementation.
By default, the SPCI-based implementation is enabled and
this is overridden if SPM_MM=1.
After: ENABLE_SPM=1 enables the SPCI-based implementation.
SPM_MM=1 enables the MM-based implementation.
The two build flags are mutually exclusive.
Note that the name of the ENABLE_SPM flag remains a bit
ambiguous - this will be improved in a subsequent patch. For this
patch the intention was to leave the name as-is so that it is
easier to track the changes that were made.
Change-Id: I8e64ee545d811c7000f27e8dc8ebb977d670608a
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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| b8e17967 | 20-Dec-2019 |
György Szing <gyorgy.szing@arm.com> |
Merge changes from topic "bs/pmf32" into integration
* changes:
pmf: Make the runtime instrumentation work on AArch32
SiP: Don't validate entrypoint if state switch is impossible |
| 5ddcbdd8 | 19-Dec-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Fix BL2 bug in dynamic configuration initialisation
This patch fixes the bug in BL2 dynamic configuration initialisation
which prevents loading NT_FW_CONFIG image (ref. GENFW-3471).
It also ad
TF-A: Fix BL2 bug in dynamic configuration initialisation
This patch fixes the bug in BL2 dynamic configuration initialisation
which prevents loading NT_FW_CONFIG image (ref. GENFW-3471).
It also adds parentheses around 'if' statement conditions to fix
Coverity defect.
Change-Id: I353566c29b84341887e13bf8098a4fedfc4e00ff
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| 992f091b | 12-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9314662314bb060f6bc02714476574da158b2a7d
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| 4e0d14f2 | 17-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "arm: gicv3: Fix compiler dependent behavior" into integration |
| 0531ada5 | 07-Nov-2019 |
Bence Szépkúti <bence.szepkuti@arm.com> |
pmf: Make the runtime instrumentation work on AArch32
Ported the pmf asm macros and the asm code in the bl31 entrypoint
necessary for the instrumentation to AArch32.
Since smc dispatch is handled b
pmf: Make the runtime instrumentation work on AArch32
Ported the pmf asm macros and the asm code in the bl31 entrypoint
necessary for the instrumentation to AArch32.
Since smc dispatch is handled by the bl32 payload on AArch32, we
provide this service only if AARCH32_SP=sp_min is set.
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>
Change-Id: Id33b7e9762ae86a4f4b40d7f1b37a90e5130c8ac
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