| b4fc0410 | 28-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "feat_state_part2" into integration
* changes:
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
refactor(t
Merge changes from topic "feat_state_part2" into integration
* changes:
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED
fix(cpufeat): context-switch: move FGT availability check to callers
feat(cpufeat): extend check_feature() to deal with min/max
refactor(cpufeat): wrap CPU ID register field isolation
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| fc8d2d39 | 17-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
At the moment we only support FEAT_TRF to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detecti
refactor(trf): enable FEAT_TRF for FEAT_STATE_CHECKED
At the moment we only support FEAT_TRF to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_TRF_FOR_NS=2), by splitting
is_feat_trf_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access TRF related registers.
Also move the context saving code from assembly to C, and use the new
is_feat_trf_supported() function to guard its execution.
The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_TRF is an ARMv8.4 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.
Change-Id: Ia97b01adbe24970a4d837afd463dc5506b7295a3
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| ff491036 | 17-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
At the moment we only support FEAT_BRBE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime dete
refactor(brbe): enable FEAT_BRBE for FEAT_STATE_CHECKED
At the moment we only support FEAT_BRBE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_BRBE_FOR_NS=2), by splitting
is_feat_brbe_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access BRBE related registers.
The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_BRBE is an ARMv9 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.
Change-Id: I5f2e2c9648300f65f0fa9a5f8e2f34e73529d053
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| f5360cfa | 17-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED
At the moment we only support FEAT_TRBE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime dete
refactor(trbe): enable FEAT_TRBE for FEAT_STATE_CHECKED
At the moment we only support FEAT_TRBE to be either unconditionally
compiled in, or to be not supported at all.
Add support for runtime detection (ENABLE_TRBE_FOR_NS=2), by splitting
is_feat_trbe_present() into an ID register reading function and a second
function to report the support status. That function considers both
build time settings and runtime information (if needed), and is used
before we access TRBE related registers.
The FVP platform decided to compile in support unconditionally (=1),
even though FEAT_TRBE is an ARMv9 feature, so is not available with the
FVP model's default command line.
Change that to the now supported dynamic option (=2), so the right
decision can be made by the code at runtime.
Change-Id: Iee7f88ea930119049543a8a4a105389997e7692c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
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| 766d78b1 | 27-Feb-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "mbedtls3_support" into integration
* changes:
feat(stm32mp1): add mbedtls-3.3 support config
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
style(crypto): add b
Merge changes from topic "mbedtls3_support" into integration
* changes:
feat(stm32mp1): add mbedtls-3.3 support config
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
style(crypto): add braces for if statement
feat(fvp): increase BL1_RW and BL2 size
feat(mbedtls): add support for mbedtls-3.3
refactor(crypto): avoid using struct mbedtls_pk_rsassa_pss_options
refactor(mbedtls): avoid including MBEDTLS_CONFIG_FILE
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| 19c1dcef | 12-Jan-2023 |
Mate Toth-Pal <mate.toth-pal@arm.com> |
fix(rme): update sample platform attestation token
Update FVP platform attestation token to comply with RMM Beta0
specification. The changes are:
- change platform implementation id claim value from
fix(rme): update sample platform attestation token
Update FVP platform attestation token to comply with RMM Beta0
specification. The changes are:
- change platform implementation id claim value from 64 to 32 bits
- change Realm Challenge
- update Hash Algorithm Identifier claim value
- add protected header
- change signing algotithm to ECDSA ES384
Change-Id: I1c5907d1a4961ce08a1408d25128de125b3f2e7f
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
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| dc2b8e80 | 23-Feb-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes from topic "panic_cleanup" into integration
* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remo
Merge changes from topic "panic_cleanup" into integration
* changes:
refactor(bl31): use elx_panic for sysreg_handler64
refactor(aarch64): rename do_panic and el3_panic
refactor(aarch64): remove weak links to el3_panic
refactor(aarch64): refactor usage of elx_panic
refactor(aarch64): cleanup HANDLE_EA_EL3_FIRST_NS usage
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| bd62ce98 | 16-Jan-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(aarch64): rename do_panic and el3_panic
Current panic call invokes do_panic which calls el3_panic, but now panic
handles only panic from EL3 anid clear separation to use lower_el_panic()
wh
refactor(aarch64): rename do_panic and el3_panic
Current panic call invokes do_panic which calls el3_panic, but now panic
handles only panic from EL3 anid clear separation to use lower_el_panic()
which handles panic from lower ELs.
So now we can remove do_panic and just call el3_panic for all panics.
Change-Id: I739c69271b9fb15c1176050877a9b0c0394dc739
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| 183adf17 | 12-Feb-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
CRYPTO_SUPPORT is enabled by default when TRUSTED_BOARD_BOOT is
enabled so usage CRYPTO_SUPPORT in conjunction with TRUSTED_BOARD_BOOT
might some
refactor(fvp): minor cleanup with TRUSTED_BOARD_BOOT
CRYPTO_SUPPORT is enabled by default when TRUSTED_BOARD_BOOT is
enabled so usage CRYPTO_SUPPORT in conjunction with TRUSTED_BOARD_BOOT
might sometime be confusing to look at.
Adding minor cleanup to make it look simpler with conditions.
No functionality changes.
Change-Id: I800524d54ea56dc27b6c6da26c75a07f5f6de984
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| dbb9c1f5 | 08-Feb-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
feat(fvp): increase BL1_RW and BL2 size
To support mbedtls3.3 increase BL1_RW and BL2 size rsa+ecdsa alg.
Increase both by one page size. In mbedtls3.3 numerous config options
have been tweaked and
feat(fvp): increase BL1_RW and BL2 size
To support mbedtls3.3 increase BL1_RW and BL2 size rsa+ecdsa alg.
Increase both by one page size. In mbedtls3.3 numerous config options
have been tweaked and made defaults[1] thus a small increase in size
can result for mbedtls-3.3
This size limitation is observed when we build TF-A with
TF_MBEDTLS_KEY_ALG=rsa+ecdsa this approach is used in juno as well,
so use similar approach for FVP.
[1]: https://github.com/Mbed-TLS/mbedtls/blob/development/docs/3.0-migration-guide.md
Change-Id: I8a423711ac50b3d615c1d9650086cdbca5051c8e
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| da04341e | 14-Feb-2023 |
Chris Kay <chris.kay@arm.com> |
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name
build: always prefix section names with `.`
Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.
This change introduces the period prefix to all specialized section
names.
BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.
Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>
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| f9e11c72 | 16-Feb-2023 |
Raef Coles <raef.coles@arm.com> |
fix(tc): unify TC ROM start addresses
Because RSS now does not map the header into the TC2 ROM, it is no
longer necessary to have the code start at 0x1000, so unify with other
TC platforms at 0x0.
fix(tc): unify TC ROM start addresses
Because RSS now does not map the header into the TC2 ROM, it is no
longer necessary to have the code start at 0x1000, so unify with other
TC platforms at 0x0.
Change-Id: I7ec34bb814865ba39678f4da0412294d4679052d
Signed-off-by: Raef Coles <raef.coles@arm.com>
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| 17797628 | 07-Feb-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fvp): update device tree with load addresses of TOS_FW config
Provided both the root and secure addresses for TOS_FW config
in case of RME enabled systems where root address is in Root
SRAM and
feat(fvp): update device tree with load addresses of TOS_FW config
Provided both the root and secure addresses for TOS_FW config
in case of RME enabled systems where root address is in Root
SRAM and secure address is in Trusted DRAM.
Non-RME systems are unaffected by this change.
Change-Id: Ifb927c90fa5a68fe5362980858b4ddc5403ac95b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| f348aec1 | 07-Feb-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp): rename the DTB info structure member
In line with the previous patch, the name of the member of the
hw_config DTB info structure has been renamed.
Change-Id: I6689e416fecd66faa515e82
refactor(fvp): rename the DTB info structure member
In line with the previous patch, the name of the member of the
hw_config DTB info structure has been renamed.
Change-Id: I6689e416fecd66faa515e820f1c4b23bcb65bfb1
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 034a2e3e | 01-Feb-2023 |
Raef Coles <raef.coles@arm.com> |
refactor(fiptool): move plat_fiptool.mk to tools
Move all plat_fiptool.mks into tools, change the logic to recursively
check for tools/fiptool/plat_fiptool/<plat_path>/plat_fiptool.mk
I.e. for a pl
refactor(fiptool): move plat_fiptool.mk to tools
Move all plat_fiptool.mks into tools, change the logic to recursively
check for tools/fiptool/plat_fiptool/<plat_path>/plat_fiptool.mk
I.e. for a platform that has the path "plat/arm/board/tc/platform.mk",
the makefile will now load the first existing file from:
- tools/fiptool/plat_fiptool/arm/board/tc/plat_fiptool.mk
- tools/fiptool/plat_fiptool/arm/board/plat_fiptool.mk
- tools/fiptool/plat_fiptool/arm/plat_fiptool.mk
This enables fiptool to support multiple platforms, or a specific one.
Remove file-copying previously being used to handle old default path.
Remove custom file cleaning in plat_fiptool.mk.
Change-Id: I95245bcf7143b329481d4394ab64f29bfe9de5ab
Signed-off-by: Raef Coles <raef.coles@arm.com>
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| e3df3ffa | 01-Feb-2023 |
Soby Mathew <soby.mathew@arm.com> |
Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration
* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): s
Merge changes I1b092bc1,Ifc2461b4,I5176caa5 into integration
* changes:
docs(rme): update RMM-EL3 Boot Manifest structure description
feat(rme): read DRAM information from FVP DTB
feat(rme): set DRAM information in Boot Manifest platform data
show more ...
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| 82685904 | 29-Dec-2022 |
AlexeiFedorov <Alexei.Fedorov@arm.com> |
feat(rme): read DRAM information from FVP DTB
This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.
Macro _RMMD_MANIFES
feat(rme): read DRAM information from FVP DTB
This patch builds on the previous patch by implementing
support for reading NS DRAM layout of FVP model from
HW_CONFIG Device tree.
Macro _RMMD_MANIFEST_VERSION is renamed to
SET_RMMD_MANIFEST_VERSION to suppress MISRA-C
"rule MC3R1.D4.5: (advisory) Identifiers in
the same name space with overlapping visibility
should be typographically unambiguous" warning
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: Ifc2461b4441a1efdd4b7c656ab4d15e62479f77b
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| be79071e | 14-Sep-2022 |
Patrik Berglund <patrik.berglund@arm.com> |
feat(morello): add support for HW_CONFIG
This patch add support to load HW_CONFIG in BL2 and pass it to
bootloader stages BL31 and BL33.
Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Cha
feat(morello): add support for HW_CONFIG
This patch add support to load HW_CONFIG in BL2 and pass it to
bootloader stages BL31 and BL33.
Signed-off-by: Patrik Berglund <patrik.berglund@arm.com>
Change-Id: I646fabed83dbca5322a59a399de5194cfef474ad
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|
| 872d8656 | 23-Jan-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(rss): add TC platform UUIDs for RSS images" into integration |
| 344e5e81 | 19-Jan-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "feat_state_rework" into integration
* changes:
feat(fvp): enable FEAT_HCX by default
refactor(context-mgmt): move FEAT_HCX save/restore into C
refactor(cpufeat): conv
Merge changes from topic "feat_state_rework" into integration
* changes:
feat(fvp): enable FEAT_HCX by default
refactor(context-mgmt): move FEAT_HCX save/restore into C
refactor(cpufeat): convert FEAT_HCX to new scheme
feat(fvp): enable FEAT_FGT by default
refactor(context-mgmt): move FEAT_FGT save/restore code into C
refactor(amu): convert FEAT_AMUv1 to new scheme
refactor(cpufeat): decouple FGT feature detection and build flags
refactor(cpufeat): check FEAT_FGT in a new way
refactor(cpufeat): move helpers into .c file, rename FEAT_STATE_
feat(aarch64): make ID system register reads non-volatile
show more ...
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| a97bfa5f | 14-Dec-2022 |
AlexeiFedorov <Alexei.Fedorov@arm.com> |
feat(rme): set DRAM information in Boot Manifest platform data
This patch adds support for setting configuration of DRAM banks
for FVP model in RMM-EL3 Boot Manifest structure.
Structure 'rmm_manife
feat(rme): set DRAM information in Boot Manifest platform data
This patch adds support for setting configuration of DRAM banks
for FVP model in RMM-EL3 Boot Manifest structure.
Structure 'rmm_manifest' is extended with 'plat_dram' structure
which contains information about platform's DRAM layout:
- number of DRAM banks;
- pointer to 'dram_bank[]' array;
- check sum: two's complement 64-bit value of the sum of
data in 'plat_dram' and 'dram_bank[] array.
Each 'dram_bank' structure holds information about DRAM
bank base address and its size. This values must be aligned
to 4KB page size.
The patch increases Boot Manifest minor version to 2 and
removes 'typedef rmm_manifest_t' as per
"3.4.15.1. Avoid anonymous typedefs of structs/enums in headers" of
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I5176caa5780e27d1e0daeb5dea3e40cf6ad5fd12
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| 028c6190 | 24-Nov-2021 |
Tony K Nadackal <tony.nadackal@arm.com> |
feat(rdn2): add platform id value for rdn2 variant 3
The RD-N2-Cfg3 platform is a variant of the RD-N2 platform with the
significant difference being the number of ITS blocks and the use of a
differ
feat(rdn2): add platform id value for rdn2 variant 3
The RD-N2-Cfg3 platform is a variant of the RD-N2 platform with the
significant difference being the number of ITS blocks and the use of a
different part number.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: Id4c5faeae44f21da79cb59540558192d0b02b124
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|
| a9896306 | 12-Nov-2022 |
Tony K Nadackal <tony.nadackal@arm.com> |
refactor(rdn2): reduce use of CSS_SGI_PLATFORM_VARIANT build flag
The core count is one of the significant difference between the various
RD-N2 platform variants. The PLAT_ARM_CLUSTER_COUNT macro de
refactor(rdn2): reduce use of CSS_SGI_PLATFORM_VARIANT build flag
The core count is one of the significant difference between the various
RD-N2 platform variants. The PLAT_ARM_CLUSTER_COUNT macro defines the
number of core/cluster for a variant. In preparation to add another
variant of RD-N2 platform, replace the use of CSS_SGI_PLATFORM_VARIANT
build flag, where applicable, with the PLAT_ARM_CLUSTER_COUNT macro.
This helps to reduce the changes required to add support for a new
variant.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I89b168308d1b5f7edd402205dd25d6c3a355e100
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| 2e124188 | 10-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
feat(fvp): enable FEAT_HCX by default
FEAT_HCX is one of the features for which Linux necessarily requires EL3
enablement, when the feature is present on a PE.
To cover the effect of different FVP
feat(fvp): enable FEAT_HCX by default
FEAT_HCX is one of the features for which Linux necessarily requires EL3
enablement, when the feature is present on a PE.
To cover the effect of different FVP command line parameters, include
the feature into the standard FVP build, but use FEAT_STATE_CHECK, to
always do runtime checks before accessing feature specific registers.
This prevents a Linux crash when the FVP is called with FEAT_HCX
enabled.
Change-Id: I01aaed15c5a6850176d092b2f0157744fe0a9e13
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
show more ...
|
| 15107daa | 10-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
feat(fvp): enable FEAT_FGT by default
FEAT_FGT is one of the features for which Linux necessarily requires EL3
enablement, when the feature is present on a PE.
To cover the effect of different FVP
feat(fvp): enable FEAT_FGT by default
FEAT_FGT is one of the features for which Linux necessarily requires EL3
enablement, when the feature is present on a PE.
To cover the effect of different FVP command line parameters, include
the feature into the standard FVP build, but use FEAT_STATE_CHECK, to
always do runtime checks before accessing feature specific registers.
This prevents a Linux crash when the FVP is called with FEAT_FGT
enabled.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I55fbb2706aefbc3ab67c476e3f8b6ea74ae0d66c
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|