| def5571d | 21-Feb-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
refactor(arm): use MBEDTLS_CONFIG_FILE macro
Used MBEDTLS_CONFIG_FILE macro for including mbedTLS
configuration.
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I374b59a31df3a
refactor(arm): use MBEDTLS_CONFIG_FILE macro
Used MBEDTLS_CONFIG_FILE macro for including mbedTLS
configuration.
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I374b59a31df3ab1e69481b2c37a6f7455a106b6e
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| 510dc79c | 18-Mar-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
refactor(corstone700): namespace MHU driver filenames
There are plans to contribute a generic MHU driver to the TF-A code
base in the short term.
In preparation for this, rename the Corstone-700 MH
refactor(corstone700): namespace MHU driver filenames
There are plans to contribute a generic MHU driver to the TF-A code
base in the short term.
In preparation for this, rename the Corstone-700 MHU driver source
files and prefix them with the name of the platform to avoid any
ambiguity or name clashes with the upcoming generic MHU driver. Also
rename the header guard accordingly.
This renaming is inline with other platform-specific MHU drivers, such
as the ones used on Broadcom [1], Socionext [2] or Amlogic [3] platforms.
[1] plat/brcm/common/brcm_mhu.h
[2] plat/socionext/synquacer/drivers/mhu/sq_mhu.h
[3] plat/amlogic/common/aml_mhu.c
Change-Id: I8a5e5b16e7c19bf931a90422dfca8f6a2a0663b4
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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| 83b3ed26 | 03-Mar-2022 |
David Vincze <david.vincze@arm.com> |
style(plat/arm/corstone1000): resolve checkpatch warnings
Change-Id: Ic8cb9b0834806675c792018e809d7ba77fbe856f
Signed-off-by: David Vincze <david.vincze@arm.com> |
| a0435105 | 22-Mar-2022 |
Soby Mathew <soby.mathew@arm.com> |
feat(rme): add dummy realm attestation key to RMMD
Add a dummy realm attestation key to RMMD, and return it on request.
The realm attestation key is requested with an SMC with the following
paramete
feat(rme): add dummy realm attestation key to RMMD
Add a dummy realm attestation key to RMMD, and return it on request.
The realm attestation key is requested with an SMC with the following
parameters:
* Fid (0xC400001B2).
* Attestation key buffer PA (the realm attestation key is copied
at this address by the monitor).
* Attestation key buffer length as input and size of realm
attesation key as output.
* Type of elliptic curve.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I12d8d98fd221f4638ef225c9383374ddf6e65eac
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| 0f9159b7 | 22-Mar-2022 |
Soby Mathew <soby.mathew@arm.com> |
feat(rme): add dummy platform token to RMMD
Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
* Fid (0xC4000
feat(rme): add dummy platform token to RMMD
Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
* Fid (0xC40001B3).
* Platform token PA (the platform token is copied at this address by
the monitor). The challenge object needs to be passed by
the caller in this buffer.
* Platform token len.
* Challenge object len.
When calling the SMC, the platform token buffer received by EL3 contains
the challenge object. It is not used on the FVP and is only printed to
the log.
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I8b2f1d54426c04e76d7a3baa6b0fbc40b0116348
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| fdb9166b | 16-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(fvp): disable reclaiming init code by default
In anticipation of Spectre BHB workaround mitigation patches, we
disable the RECLAIM_INIT_CODE for FVP platform. Since the spectre
BHB mitigation wo
fix(fvp): disable reclaiming init code by default
In anticipation of Spectre BHB workaround mitigation patches, we
disable the RECLAIM_INIT_CODE for FVP platform. Since the spectre
BHB mitigation workarounds inevitably increase the size of the various
segments due to additional instructions and/or macros, these segments
cannot be fit in the existing memory layout designated for BL31 image.
The issue is specifically seen in complex build configs for FVP
platform. One such config has TBB with Dual CoT and test secure
payload dispatcher(TSPD) enabled. Even a small increase in individual
segment size in order of few bytes might lead to build fails due to
alignment requirements(PAGE_ALIGN to 4KB).
This is needed to workaround the following build failures observed
across multiple build configs:
aarch64-none-elf-ld.bfd: BL31 init has exceeded progbits limit.
aarch64-none-elf-ld.bfd: /work/workspace/workspace/tf-worker_ws_2/trusted_firmware/build/fvp/debug/bl31/bl31.elf section coherent_ram will not fit in region RAM
aarch64-none-elf-ld.bfd: BL31 image has exceeded its limit.
aarch64-none-elf-ld.bfd: region RAM overflowed by 4096 bytes
Change-Id: Idfab539e9a40f4346ee11eea1e618c97e93e19a1
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| ddbf43b4 | 22-Apr-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(fvp_r): update set_config_info function call
Pass NS-load address as ~0UL to the 'set_config_info' function while
updating FW_CONFIG device tree information since it is always loaded
into s
refactor(fvp_r): update set_config_info function call
Pass NS-load address as ~0UL to the 'set_config_info' function while
updating FW_CONFIG device tree information since it is always loaded
into secure memory.
Change-Id: I64e8531e0ad5cda63f14d838efb9da9cf20beea8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 7c6d460e | 10-Mar-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(fvp): op-tee sp manifest doesn't map gicd" into integration |
| 0c55c103 | 01-Feb-2022 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
fix(fvp): FCONF Trace Not Shown
Updating call order for arm_console_boot_init() and arm_bl31_early_platform_setup().
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: If932fff2
fix(fvp): FCONF Trace Not Shown
Updating call order for arm_console_boot_init() and arm_bl31_early_platform_setup().
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: If932fff2ee4282a0aacf8751fa81e7665b886467
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| 69cde5cd | 25-May-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
fix(fvp): op-tee sp manifest doesn't map gicd
Following I2d274fa897171807e39b0ce9c8a28824ff424534:
Remove GICD registers S2 mapping from OP-TEE partition when it runs in a
secure partition on top of
fix(fvp): op-tee sp manifest doesn't map gicd
Following I2d274fa897171807e39b0ce9c8a28824ff424534:
Remove GICD registers S2 mapping from OP-TEE partition when it runs in a
secure partition on top of Hafnium.
The partition is not meant to access the GIC directly but use the
Hafnium provided interfaces.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I1a38101f6ae9911662828734a3c9572642123f32
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| 92537e17 | 28-Feb-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(measured-boot): add RMM entry to event_log_metadata" into integration |
| 80b895ca | 23-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(board/rdedmunds): add support for rdedmunds variant" into integration |
| f4e3e1e8 | 10-Jan-2022 |
Tamas Ban <tamas.ban@arm.com> |
fix(measured-boot): add RMM entry to event_log_metadata
Platforms which support Realm world cannot boot up
properly if measured boot is enabled at build time.
An assertions occurs due to the missing
fix(measured-boot): add RMM entry to event_log_metadata
Platforms which support Realm world cannot boot up
properly if measured boot is enabled at build time.
An assertions occurs due to the missing RMM entry
in the event_log_metadata array.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I172f10a440797f7c9e1bc79dc72242b40c2521ea
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| 23ac80cc | 17-Feb-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(fvp): extend memory map to include all DRAM memory regions" into integration |
| e8035421 | 23-Dec-2021 |
Federico Recanati <federico.recanati@arm.com> |
fix(fvp): extend memory map to include all DRAM memory regions
Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
w
fix(fvp): extend memory map to include all DRAM memory regions
Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
whole address space.
Configuring all of them to allow tests to access memory also in those
higher memory regions.
FVP memory map:
https://developer.arm.com/documentation/100964/1116/Base-Platform/Base---memory/Base-Platform-memory-map
Note that last row is wrong, describing a non-existing 56bit address,
all region labels should be shifted upward.
Issue has been reported and next release will be correct.
Change-Id: I695fe8e24aff67d75e74635ba32a133342289eb4
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
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| ef515f0d | 19-Aug-2021 |
Tony K Nadackal <tony.nadackal@arm.com> |
feat(board/rdedmunds): add support for rdedmunds variant
Add initial support for RD-Edmunds platform. This platform is considered
as a variant of RD-N2 platform with only major change being the CPU
feat(board/rdedmunds): add support for rdedmunds variant
Add initial support for RD-Edmunds platform. This platform is considered
as a variant of RD-N2 platform with only major change being the CPU
which is Demeter instead of Neoverse-N2.
Signed-off-by: Tony K Nadackal <tony.nadackal@arm.com>
Change-Id: I939d9eac652fa9e76ad002ee5e6107aa79baa013
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| cf89fd57 | 27-Oct-2021 |
Satish Kumar <satish.kumar01@arm.com> |
feat(corstone1000): identify bank to load fip
Secure enclave decides the boot bank based on the firmware update
state of the system and updates the boot bank information at a given
location in the f
feat(corstone1000): identify bank to load fip
Secure enclave decides the boot bank based on the firmware update
state of the system and updates the boot bank information at a given
location in the flash. In this commit, bl2 reads the given flash
location to indentify the bank from which it should load fip from.
Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I7f0f4ffc97189c9deb99db44afcd966082ffbf21
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| 15594501 | 20-Sep-2021 |
Satish Kumar <satish.kumar01@arm.com> |
fix(corstone1000): change base address of FIP in the flash
More space in the flash is reserved up front for metadata
parser and UEFI variables. That requires change in the flash
base address of wher
fix(corstone1000): change base address of FIP in the flash
More space in the flash is reserved up front for metadata
parser and UEFI variables. That requires change in the flash
base address of where images are present.
Signed-off-by: Satish Kumar <satish.kumar01@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: Ieaabe09374d707de18d36505c69b6c9a8c2ec2e9
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| a599c80d | 17-Nov-2021 |
Emekcan Aras <Emekcan.Aras@arm.com> |
feat(corstone1000): implement platform specific psci reset
This change implements platform specific psci reset
for the corstone1000.
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Signed-off-by
feat(corstone1000): implement platform specific psci reset
This change implements platform specific psci reset
for the corstone1000.
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Change-Id: I25f77234506416c3376ff4a028f6ea40ebe68437
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| 854d1c10 | 13-Oct-2021 |
Arpita S.K <Arpita.S.K@arm.com> |
feat(corstone1000): made changes to accommodate 3MB for optee
These changes are required to accommodate 3MB for OP-TEE and this
is required for SP's part of optee
Added size macro's for better reada
feat(corstone1000): made changes to accommodate 3MB for optee
These changes are required to accommodate 3MB for OP-TEE and this
is required for SP's part of optee
Added size macro's for better readability of the code
Moved uboot execution memory from CVM to DDR
Change-Id: I16657c6e336fe7c0fffdee1617d10af8a2c76732
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
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| 0260eb0d | 19-Jan-2022 |
Vishnu Banavath <vishnu.banavath@arm.com> |
build(corstone1000): rename diphda to corstone1000
diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda corstone1000.
Change-Id
build(corstone1000): rename diphda to corstone1000
diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda corstone1000.
Change-Id: I330f3a112d232b99b4721b6bf0236253b068dbba
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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| efeb4380 | 09-Aug-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
feat(rdn2): add board support for rdn2cfg2 variant
Add board support for variant 2 of RD-N2 platform which is a four chip
variant with 4 cores on each chip. The "CSS_SGI_PLATFORM_VARIANT" value
is 2
feat(rdn2): add board support for rdn2cfg2 variant
Add board support for variant 2 of RD-N2 platform which is a four chip
variant with 4 cores on each chip. The "CSS_SGI_PLATFORM_VARIANT" value
is 2 for multi-chip variant. The "CSS_SGI_CHIP_COUNT_MACRO" can be in
the range [1, 4] for multi-chip variant.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I6412106e80e2f17704c796226c2ee9fe808705ba
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| 14714755 | 07-Dec-2021 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
feat(cpu): add library support for Poseidon CPU
This patch adds the basic CPU library code to support the Poseidon CPU
in TF-A. Poseidon is derived from HunterELP core, an implementation of
v9.2 arc
feat(cpu): add library support for Poseidon CPU
This patch adds the basic CPU library code to support the Poseidon CPU
in TF-A. Poseidon is derived from HunterELP core, an implementation of
v9.2 architecture. Currently, Hunter CPU the predecessor to HunterELP,
is supported in TF-A. Accordingly the Hunter CPU library code has been
as the base and adapted here.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I406b4de156a67132e6a5523370115aaac933f18d
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| b1963003 | 25-Jan-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "decouple-tb-mb" into integration
* changes:
refactor(renesas): disable CRYPTO_SUPPORT option
refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot
refactor(me
Merge changes from topic "decouple-tb-mb" into integration
* changes:
refactor(renesas): disable CRYPTO_SUPPORT option
refactor(fvp): avoid Measured-Boot dependency on Trusted-Boot
refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot
build: introduce CRYPTO_SUPPORT build option
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| 59da207e | 13-Oct-2021 |
Davidson K <davidson.kumaresan@arm.com> |
feat(tc): enable tracing
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan
feat(tc): enable tracing
Total Compute has ETE and TRBE tracing components and they have
to be enabled to capture the execution trace of the processor.
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Change-Id: I3c86c11be2c655a61ecefa3eb2e4e3951577a113
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