1# 2# Copyright (c) 2018-2022, Arm Limited. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7 8N1SDP_BASE := plat/arm/board/n1sdp 9 10INTERCONNECT_SOURCES := ${N1SDP_BASE}/n1sdp_interconnect.c 11 12PLAT_INCLUDES := -I${N1SDP_BASE}/include 13 14 15N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S 16 17# GIC-600 configuration 18GICV3_SUPPORT_GIC600 := 1 19GICV3_IMPL_GIC600_MULTICHIP := 1 20 21# Include GICv3 driver files 22include drivers/arm/gic/v3/gicv3.mk 23 24N1SDP_GIC_SOURCES := ${GICV3_SOURCES} \ 25 plat/common/plat_gicv3.c \ 26 plat/arm/common/arm_gicv3.c \ 27 28PLAT_BL_COMMON_SOURCES := ${N1SDP_BASE}/n1sdp_plat.c \ 29 ${N1SDP_BASE}/aarch64/n1sdp_helper.S 30 31BL1_SOURCES := ${N1SDP_CPU_SOURCES} \ 32 ${INTERCONNECT_SOURCES} \ 33 ${N1SDP_BASE}/n1sdp_err.c \ 34 ${N1SDP_BASE}/n1sdp_trusted_boot.c \ 35 ${N1SDP_BASE}/n1sdp_bl1_setup.c \ 36 drivers/arm/sbsa/sbsa.c 37 38BL2_SOURCES := ${N1SDP_BASE}/n1sdp_security.c \ 39 ${N1SDP_BASE}/n1sdp_err.c \ 40 ${N1SDP_BASE}/n1sdp_trusted_boot.c \ 41 lib/utils/mem_region.c \ 42 ${N1SDP_BASE}/n1sdp_bl2_setup.c \ 43 drivers/arm/css/sds/sds.c 44 45BL31_SOURCES := ${N1SDP_CPU_SOURCES} \ 46 ${INTERCONNECT_SOURCES} \ 47 ${N1SDP_GIC_SOURCES} \ 48 ${N1SDP_BASE}/n1sdp_bl31_setup.c \ 49 ${N1SDP_BASE}/n1sdp_topology.c \ 50 ${N1SDP_BASE}/n1sdp_security.c \ 51 drivers/arm/css/sds/sds.c 52 53FDT_SOURCES += fdts/${PLAT}-single-chip.dts \ 54 fdts/${PLAT}-multi-chip.dts \ 55 ${N1SDP_BASE}/fdts/n1sdp_fw_config.dts \ 56 ${N1SDP_BASE}/fdts/n1sdp_tb_fw_config.dts 57 58FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_fw_config.dtb 59TB_FW_CONFIG := ${BUILD_PLAT}/fdts/n1sdp_tb_fw_config.dtb 60 61# Add the FW_CONFIG to FIP and specify the same to certtool 62$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 63# Add the TB_FW_CONFIG to FIP and specify the same to certtool 64$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 65 66# Setting to 0 as no NVCTR in N1SDP 67N1SDP_FW_NVCTR_VAL := 0 68TFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL} 69NTFW_NVCTR_VAL := ${N1SDP_FW_NVCTR_VAL} 70 71# Add N1SDP_FW_NVCTR_VAL 72$(eval $(call add_define,N1SDP_FW_NVCTR_VAL)) 73 74# TF-A not required to load the SCP Images 75override CSS_LOAD_SCP_IMAGES := 0 76 77override NEED_BL2U := no 78 79# 32 bit mode not supported 80override CTX_INCLUDE_AARCH32_REGS := 0 81 82override ARM_PLAT_MT := 1 83 84# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 85# SCP during power management operations and for SCP RAM Firmware transfer. 86CSS_USE_SCMI_SDS_DRIVER := 1 87 88# System coherency is managed in hardware 89HW_ASSISTED_COHERENCY := 1 90 91# When building for systems with hardware-assisted coherency, there's no need to 92# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. 93USE_COHERENT_MEM := 0 94 95# Enable the flag since N1SDP has a system level cache 96NEOVERSE_Nx_EXTERNAL_LLC := 1 97include plat/arm/common/arm_common.mk 98include plat/arm/css/common/css_common.mk 99include plat/arm/board/common/board_common.mk 100