Merge "fix(tc): fix BL31 size for PLATFORM_TEST" into integration

fix(tc): fix BL31 size for PLATFORM_TEST

We need to account for the extra large BL31
when PLATFORM_TEST_TFM_TESTSUITE is enabled.

Change-Id: Ifebf839a848f3a859898f920e42e0f39cca7d2cf
Signed-off-by:

fix(tc): fix BL31 size for PLATFORM_TEST

We need to account for the extra large BL31
when PLATFORM_TEST_TFM_TESTSUITE is enabled.

Change-Id: Ifebf839a848f3a859898f920e42e0f39cca7d2cf
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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refactor(el3-runtime): generalise sysreg trapping

On a first look, the system register trapping code is quite
straightforward - match the register and call a handler. But looking a
bit more closely,

refactor(el3-runtime): generalise sysreg trapping

On a first look, the system register trapping code is quite
straightforward - match the register and call a handler. But looking a
bit more closely, with the intention of adding a new one, it isn't -
matching is based on opaque magic numbers and handlers have a lot of
duplication.

This patch tries to resolve both of these by hoisting common
functionality up towards common code and using S3 encodings for the
register matching. It also moves things around a bit to make them more
reusable in future.

Change-Id: Ia69289bfb16615312cc7adcc5cc3e319174b1bf0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(tc): add fpga flash regions in spmc manifest

Add fpga flash regions in spmc manifest so that fpga flash
can be used from secure partitions.

Change-Id: I14e130d1f840d63372d3ec937f0a8eca74a43da4

feat(tc): add fpga flash regions in spmc manifest

Add fpga flash regions in spmc manifest so that fpga flash
can be used from secure partitions.

Change-Id: I14e130d1f840d63372d3ec937f0a8eca74a43da4
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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feat(tc): support 6mid2big CPU topology for FPGA

Add config option to enable 6-mid/2-big CPU topology which replaces
little core with mid cores, this config is only applicable to
TC4-FPGA.

Change-I

feat(tc): support 6mid2big CPU topology for FPGA

Add config option to enable 6-mid/2-big CPU topology which replaces
little core with mid cores, this config is only applicable to
TC4-FPGA.

Change-Id: I5ba73743203445f95a0b7057305488c2f7a0fee4
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(tc): don't use non-secure UART

Align FVP and FPGA UART usage

Change-Id: If574683c53dbc245b2d4978998d12cbd640c02b7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Ryan Ever

fix(tc): don't use non-secure UART

Align FVP and FPGA UART usage

Change-Id: If574683c53dbc245b2d4978998d12cbd640c02b7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(tc): fix the platform topology

The platform topology is used by PSCI for power state machine
management. The TC platform has the affinity levels:

- CPU : affinity level 0
- Cluster : af

fix(tc): fix the platform topology

The platform topology is used by PSCI for power state machine
management. The TC platform has the affinity levels:

- CPU : affinity level 0
- Cluster : affinity level 1
- System : affinity level 2

Correct PLAT_MAX_PWR_LVL and tc_pd_tree_desc to reflect the three levels
of affinity.

We also need to calculate the right number for power domains, in the end
the PSCI will allocate corresponding structures for maintain these power
domains.

After these extending, add tc_security.c into building list to dismiss
building failure.

Change-Id: I575f84c165fde1c8065437f7d1ec261bb0c7b57a
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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feat(tc): support buildroot ddk runtime integration

- Updated the data fs load address to align with the new memory
layout requirements.
- Defined and integrated the Buildroot memory layout into RAM

feat(tc): support buildroot ddk runtime integration

- Updated the data fs load address to align with the new memory
layout requirements.
- Defined and integrated the Buildroot memory layout into RAM.

Change-Id: If6216150f4a0e97acda6ec4dbf5782ffc48bae23
Signed-off-by: Quoc Khanh Le <quockhanh.le@arm.com>
Signed-off-by: Mohanprasath Ramamoorthy <mohanprasath.ramamoorthy@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge "fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID" into integration

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch m

fix(cpus)!: make ERRATA_SME_POWER_DOWN work with the recommended state ID

The ERRATA_SME_POWER_DOWN flag doesn't account for the recommended state
ID encoding, only for the default one. This patch makes it work by
removing the generic flag and incorporating the functionality into the
CPU and platform layers.

The ERRATA_SME_POWER_DOWN is an awkward fix in generic code to a
platform problem. The PSCI layer shouldn't care about any CPU's inner
workings but it does. This isn't ideal once the issue is fixed since
we'll have to carry the "legacy" fix in generic code.

This patch is marked as breaking since the ERRATA_SME_POWER_DOWN flag is
removed and a couple of lines are required if CPU hotplug encounters a
powerdown with live SME state (CPU suspend will work as before). This
will get discovered with a panic at EL3 so this patch leaves a comment
to be able to trace it back.

Change-Id: Ia52865f527e81a8be3727093ed370901e55c5fef
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(gic): init the GIC before the platform with a hook

While GIC setup is generic across platforms, its usage is not. Some
platforms won't use it at EL3, while others need to configure interrupts
(l

fix(gic): init the GIC before the platform with a hook

While GIC setup is generic across platforms, its usage is not. Some
platforms won't use it at EL3, while others need to configure interrupts
(like RAS) in the standard platform hooks. To do that, the GIC needs to
be set up and ready to use before calling the platform hooks but
currently that is only done after. Annoyingly, a handful of platforms
need to set their GIC up before initialising it necessitating the
platform hooks to be called before GIC init.

This patch resolves this contradiction by moving the general GIC setup
calls to before the platform hooks and adding a GIC-specific platform
hook just before GIC per CPU init. This way both types of platforms can
do their business at the same time.

Change-Id: I361f587ab4603162ee880addb074800cbbb97b49
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(tc): add missing platform.h include

This include is required for plat_panic_handler.

Change-Id: Ifad8ff294c396929979969a0115866030342f1f5
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-dr

fix(tc): add missing platform.h include

This include is required for plat_panic_handler.

Change-Id: Ifad8ff294c396929979969a0115866030342f1f5
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(tc): use SFCP PSA call instead of RSE comms

Add the platform specific implementation for SFCP (the implementation of
the functions in sfcp_platform.h). This includes functions which specify
the

feat(tc): use SFCP PSA call instead of RSE comms

Add the platform specific implementation for SFCP (the implementation of
the functions in sfcp_platform.h). This includes functions which specify
the device structures and also the routing tables.

Note that, because initially the SFCP stack is only used to make PSA
calls to the RSE, routing is only implemented for the TF-A <-> RSE
nodes. The only MHU devices defined in the SFCP platform implementation
are for this link and all other routes, as defined in the routing table,
as invalid.

This patch also removes compilation of RSE comms in favour of SFCP for
TC.

Change-Id: I432b05b2955c790c4a5ecff04764605c6ff0ceea
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(tc): add tc_sfcp.c

Add the SFCP platform configuration file for TC. This file defines the
functions in declared in sfcp_platform.h; these are used in
sfcp_link_hal.c.

Note that these functions

feat(tc): add tc_sfcp.c

Add the SFCP platform configuration file for TC. This file defines the
functions in declared in sfcp_platform.h; these are used in
sfcp_link_hal.c.

Note that these functions are expected to be implemented by any TF-A
platform which makes use of the SFCP library, they define the underlying
device driver structures and the routing layout of the platform.

Change-Id: I4af7371decd1faabbd0ed7bc186339668a0c6b1a
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout

fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout is not included when building FVP.
FVP's do not require a physical carveout to
emulate MTE, so we can save the memory.
- Add memory map diagrams to platform_def.h
- Tidy up existing memory map macros.

Change-Id: I4d31aa27e470344d4ed6469939331d0e2ced9d54
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which v

fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which verified this feature.

BREAKING CHANGE: platforms can no longer retrieve the host ROTPK from
the RSE as these are no longer provisioned.

Change-Id: I2c852855e53c36e77f639f17f4c181290d95ccff
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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Merge "fix(tc): correct register write in rng trap handler" into integration

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without en

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without enabling
FEAT_AMUv1p1. As a result, the AMU_RESTRICT_COUNTERS may not take
effect, making this configuration potentially insecure.

Fix this by adding a constraints and rejigging auxiliary counter enables
such that they only happen when FEAT_AMUv1p1 has been enabled so that's
more apparent.

Change-Id: I5b5061d603013598f07d70401d68915c016a1a1b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_r

fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_reg() instead of the register offset which resulted in the
incorrect register being modified.

Change-Id: I1063b7d1e17037f60a745ceb6653cd3419ec6a67
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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Merge "fix(tc): force specifying TARGET_PLATFORM" into integration

fix(tc): force specifying TARGET_PLATFORM

tc platform.mk has assumptions about TARGET_PLATFORM to be properly
defined.

For PLAT=tc if not specifying TARGET_PLATFORM on build command line, it
emits

fix(tc): force specifying TARGET_PLATFORM

tc platform.mk has assumptions about TARGET_PLATFORM to be properly
defined.

For PLAT=tc if not specifying TARGET_PLATFORM on build command line, it
emits the cryptic error message:

expr: syntax error: unexpected argument \u20182\u2019
plat/arm/board/tc/platform.mk:75: *** Platform tc is no longer available.. Stop.

Add an assert such that the error becomes:

plat/arm/board/tc/platform.mk:9: *** TARGET_PLATFORM must not be empty. Stop.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: If53a01b537768a806495d8dc1c5096059eafa490

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fix(dice): prevent compiler warnings

LTO builds make the compiler observe possible unitialised accesses.
That's not the case, but calm it down with a 0. It also doesn't like the
declaration mismatch

fix(dice): prevent compiler warnings

LTO builds make the compiler observe possible unitialised accesses.
That's not the case, but calm it down with a 0. It also doesn't like the
declaration mismatch in tc so bring it in line.

Change-Id: I0276257d05d1cb1d4f7e1e0d914c48c8ab3d308d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(arm): don't override the gic redistributor frames" into integration

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whet

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whether the platform might want to use something different. The thinking
was to provide a default and then let each platform override it, however
the order was swapped.

To fix this, put the gic_set_gicr_frames() in bl31_platform_setup()
rather than arm_bl31_platform_setup(). This way, platforms that use the
default can still enjoy it automatically pulled in from common code,
platforms that need fully custom gicr_frames can simply set it, and
platforms that override bl31_platform_setup() for unrelated reasons only
have to redo the call to gic_set_gicr_frames(). This has a tiny benefit
over the old approach in that there will never be 2 gicr_frames arrays.

Change-Id: I734737d3bd37ddbb3286abcdd92c88676c68cdc3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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