fix(tc): add missing platform.h include

This include is required for plat_panic_handler.

Change-Id: Ifad8ff294c396929979969a0115866030342f1f5
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-dr

fix(tc): add missing platform.h include

This include is required for plat_panic_handler.

Change-Id: Ifad8ff294c396929979969a0115866030342f1f5
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(tc): use SFCP PSA call instead of RSE comms

Add the platform specific implementation for SFCP (the implementation of
the functions in sfcp_platform.h). This includes functions which specify
the

feat(tc): use SFCP PSA call instead of RSE comms

Add the platform specific implementation for SFCP (the implementation of
the functions in sfcp_platform.h). This includes functions which specify
the device structures and also the routing tables.

Note that, because initially the SFCP stack is only used to make PSA
calls to the RSE, routing is only implemented for the TF-A <-> RSE
nodes. The only MHU devices defined in the SFCP platform implementation
are for this link and all other routes, as defined in the routing table,
as invalid.

This patch also removes compilation of RSE comms in favour of SFCP for
TC.

Change-Id: I432b05b2955c790c4a5ecff04764605c6ff0ceea
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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feat(tc): add tc_sfcp.c

Add the SFCP platform configuration file for TC. This file defines the
functions in declared in sfcp_platform.h; these are used in
sfcp_link_hal.c.

Note that these functions

feat(tc): add tc_sfcp.c

Add the SFCP platform configuration file for TC. This file defines the
functions in declared in sfcp_platform.h; these are used in
sfcp_link_hal.c.

Note that these functions are expected to be implemented by any TF-A
platform which makes use of the SFCP library, they define the underlying
device driver structures and the routing layout of the platform.

Change-Id: I4af7371decd1faabbd0ed7bc186339668a0c6b1a
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout

fix(tc): configure mte addresses and sizes

- Use the carveout address specified by the MCN Top-level
design spec. The total size of the MTE carveout is 1/32 of
the available DRAM.
- MTE carveout is not included when building FVP.
FVP's do not require a physical carveout to
emulate MTE, so we can save the memory.
- Add memory map diagrams to platform_def.h
- Tidy up existing memory map macros.

Change-Id: I4d31aa27e470344d4ed6469939331d0e2ced9d54
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which v

fix(rse): remove host ROTPK support and test

Remove support for the retrieving a host ROTPK from the RSE, as the RSE
no longer has host ROTPKs provisioned by default. Also remove the TC
test which verified this feature.

BREAKING CHANGE: platforms can no longer retrieve the host ROTPK from
the RSE as these are no longer provisioned.

Change-Id: I2c852855e53c36e77f639f17f4c181290d95ccff
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

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Merge "fix(tc): correct register write in rng trap handler" into integration

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without en

fix(cpufeat): require FEAT_AMUv1p1 to enable the auxiliary counters

The auxiliary counters are a feature of FEAT_AMUv1p1 but it's possible
to enable them (ENABLE_AMU_AUXILIARY_COUNTERS=1) without enabling
FEAT_AMUv1p1. As a result, the AMU_RESTRICT_COUNTERS may not take
effect, making this configuration potentially insecure.

Fix this by adding a constraints and rejigging auxiliary counter enables
such that they only happen when FEAT_AMUv1p1 has been enabled so that's
more apparent.

Change-Id: I5b5061d603013598f07d70401d68915c016a1a1b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_r

fix(tc): correct register write in rng trap handler

Fix the TC rng trap handler to write the random value to the correct
GP register. The handler previously passed the register number to
write_ctx_reg() instead of the register offset which resulted in the
incorrect register being modified.

Change-Id: I1063b7d1e17037f60a745ceb6653cd3419ec6a67
Signed-off-by: Aditya Deshpande <aditya.deshpande@arm.com>

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Merge "fix(tc): force specifying TARGET_PLATFORM" into integration

fix(tc): force specifying TARGET_PLATFORM

tc platform.mk has assumptions about TARGET_PLATFORM to be properly
defined.

For PLAT=tc if not specifying TARGET_PLATFORM on build command line, it
emits

fix(tc): force specifying TARGET_PLATFORM

tc platform.mk has assumptions about TARGET_PLATFORM to be properly
defined.

For PLAT=tc if not specifying TARGET_PLATFORM on build command line, it
emits the cryptic error message:

expr: syntax error: unexpected argument \u20182\u2019
plat/arm/board/tc/platform.mk:75: *** Platform tc is no longer available.. Stop.

Add an assert such that the error becomes:

plat/arm/board/tc/platform.mk:9: *** TARGET_PLATFORM must not be empty. Stop.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: If53a01b537768a806495d8dc1c5096059eafa490

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fix(dice): prevent compiler warnings

LTO builds make the compiler observe possible unitialised accesses.
That's not the case, but calm it down with a 0. It also doesn't like the
declaration mismatch

fix(dice): prevent compiler warnings

LTO builds make the compiler observe possible unitialised accesses.
That's not the case, but calm it down with a 0. It also doesn't like the
declaration mismatch in tc so bring it in line.

Change-Id: I0276257d05d1cb1d4f7e1e0d914c48c8ab3d308d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(arm): don't override the gic redistributor frames" into integration

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assist

refactor(arm/common): gate coherency behind flag

Introduce a macro guard so platform coherency functions are only
compiled when HW_ASSISTED_COHERENCY is 0 (disabled). Many platforms
enable HW-assisted coherency by default, so compiling empty
definitions is unnecessary.

This refactor removes those empty functions for Arm CSS platforms.

Change-Id: I102ead46960e9da2d8b968f60cbfd3e5e5da1096
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>

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fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whet

fix(arm): don't override the gic redistributor frames

Patch 75170704c made an oversight - it would provide a default value for
the gicr_frames variable but would always set to it, regardless of
whether the platform might want to use something different. The thinking
was to provide a default and then let each platform override it, however
the order was swapped.

To fix this, put the gic_set_gicr_frames() in bl31_platform_setup()
rather than arm_bl31_platform_setup(). This way, platforms that use the
default can still enjoy it automatically pulled in from common code,
platforms that need fully custom gicr_frames can simply set it, and
platforms that override bl31_platform_setup() for unrelated reasons only
have to redo the call to gic_set_gicr_frames(). This has a tiny benefit
over the old approach in that there will never be 2 gicr_frames arrays.

Change-Id: I734737d3bd37ddbb3286abcdd92c88676c68cdc3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts

refactor(tc): neaten platform code after TC2 removal

Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.

Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

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Merge changes from topic "ja/ffa_v1_3" into integration

* changes:
feat(tc): bump SPMC version to FF-A v1.3 TC platform
feat(fvp): bump the SPMC version
feat(ff-a): bump SPMD FF-A version

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/docu

chore(tc): align core names to Arm Lumex

Adopt core names aligned to Arm Lumex [1]

Nevis => C1-Nano
Gelas => C1-Pro
Travis => C1-Ultra
Alto => C1-Premium

C1-Pro TRM: https://developer.arm.com/documentation/107771/0102/
C1-Ultra TRM: https://developer.arm.com/documentation/108014/0100/
C1-Premium TRM: https://developer.arm.com/documentation/109416/0100/
C1-Nano TRM: https://developer.arm.com/documentation/107753/0001/

[1]:
https://www.arm.com/product-filter?families=c1%20cpus
https://www.arm.com/products/mobile/compute-subsystems/lumex

Signed-off-by: Min Yao Ng <minyao.ng@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Id4b487ef6a6fd1b00b75b09c5d06d81bce50a15d
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(tc): bump SPMC version to FF-A v1.3 TC platform

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I196a0eb1bedb8bcc35b4524f04ea75f8c832a7f9

feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link

feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I6e97954a1ce91fdbda4edcdba5ccfa1d7c8ff475

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feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

T

feat(psci): make pabandon support generic

Support for aborted powerdowns does not require much dedicated code.
Rather, it is largely a matter of orchestrating things to happen in the
right order.

The only exception to this are older secure world dispatchers, which
assume that a CPU_SUSPEND call will be terminal and therefore can
clobber context. This was patched over in common code and hidden behind
a flag. This patch moves this to the dispatchers themselves.

Dispatchers that don't register svc_suspend{_finish} are unaffected.
Those that do must save the NS context before clobbering it and
restoring in only in case of a pabandon. Due to this operation being
non-trivial, this patch makes the assumption that these dispatchers will
only be present on hardware that does not support pabandon and therefore
does not add any contexting for them. In case this assumption ever
changes, asserts are added that should alert us of this change.

Change-Id: I94a907515b782b4d2136c0d274246cfe1d567c0e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(tc): add support for configuring DSU settings

This patch allows tc platforms to update DSU
CLUSTERPWRDN_EL1 and CLUSTERPWRCTLR_EL1 settings.
TC22 and TC23 use the DSU-120. Currently
we use the

feat(tc): add support for configuring DSU settings

This patch allows tc platforms to update DSU
CLUSTERPWRDN_EL1 and CLUSTERPWRCTLR_EL1 settings.
TC22 and TC23 use the DSU-120. Currently
we use the reset values as default settings as
per the DSU-120 TRM.

Reference: https://developer.arm.com/documentation/102547/0201

Change-Id: I48e0b5bd5881612e9b8b804948260f69c25c34d9
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also

feat(dsu): support power control and autonomous powerdown config

This patch allows platforms to enable certain DSU settings
to ensure memory retention and control over
cache power requests. We also move the driver out of css
into drivers/arm. Platforms can configure the
CLUSTERPWRCTLR and CLUSTERPWRDN registers [1] to improve
power efficiency.

These registers enable finer-grained control of
DSU power state transitions, including
powerdown and retention.

IMP_CLUSTERPWRCTLR_EL1 provides:
- Functional retention: Allows configuration of the
duration of inactivity before the DSU uses
CLUSTERPACTIVE to request functional retention.

- Cache power request: These bits are output on
CLUSTERPACTIVE[19:16] to indicate to the power controller
which cache portions must remain powered.

IMP_CLUSTERPWRDN_EL1 includes:
- Powerdown: Triggers full cluster powerdown, including
control logic.

- Memory retention: Requests memory retention mode,
keeping L3 RAM contents while powering off
the rest of the DSU.

The DSU-120 TRM [2] provides the full field definitions,
which are used as references in the `dsu_driver_data` structure.

References:
[1]: https://developer.arm.com/documentation/100453/latest/
[2]: https://developer.arm.com/documentation/102547/0201/?lang=en

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I2eba808b8f2a27797782a333c65dd092b03208fe

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Merge "chore(tc): remove TC2 platform variant" into integration

refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos(

refactor: convert arm platforms to use the generic GIC driver

This reduces the code the platforms have to carry and makes their build
rules a bit simpler.

The main benefit is that plat_my_core_pos() no longer needs to be called
within the driver, helping with performance a bit.

Change-Id: I0b0d1d36d20d67c41c8c9dc14ade11bda6d4a6af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is

refactor: make arm_gicv2.c and arm_gicv3.c common

These files were meant to be platform specific, but they are generic
enough that a range of platforms find them useful. However, refactoring
them is difficult as their use is platform specific. So copy them to a
generic place and redirect platforms to them.

The new copies will remain for compatibility for platforms that don't
want to or can't take up upcoming refactors and the old copies can be
drastically refactored to make them more widely applicable.

Change-Id: I056c8710cdda4d8a81b324d392762c29e02cdae1
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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